RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
☆160Mar 19, 2018Updated 8 years ago
Alternatives and similar repositories for NoCRouter
Users that are interested in NoCRouter are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Network on Chip Implementation written in SytemVerilog☆216Aug 27, 2022Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆201Nov 18, 2024Updated last year
- A verilog implementation for Network-on-Chip☆88Feb 3, 2018Updated 8 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 10 years ago
- Network on Chip for MPSoC☆30Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆90Oct 25, 2014Updated 12 years ago
- Network on Chip Simulator☆342Oct 29, 2026Updated last week
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- ☆43Apr 28, 2019Updated 7 years ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆187Dec 14, 2019Updated 6 years ago
- ☆15Oct 27, 2026Updated last week
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆24Nov 2, 2015Updated 11 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- HLS for Networks-on-Chip☆40Feb 18, 2021Updated 5 years ago
- An Open Source Link Protocol and Controller☆30Aug 1, 2021Updated 5 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- ☆15Jul 28, 2022Updated 4 years ago
- 🎞️ NoC router in Verilog with FIFO☆15Sep 1, 2022Updated 4 years ago
- Ratatoskr NoC Simulator☆30Apr 13, 2021Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Mar 8, 2021Updated 5 years ago
- SystemVerilog file list pruner☆19Oct 19, 2026Updated 2 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆18Apr 12, 2020Updated 6 years ago
- Tenstorrent reference design (harness) for the Open Chiplet Atlas (OCA) architecture☆23Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆70Oct 29, 2026Updated last week
- ☆27Oct 25, 2026Updated last week
- A Fast, Low-Overhead On-chip Network☆371Updated this week
- OpenSoC Fabric - A Network-On-Chip Generator☆179Jun 18, 2020Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆41Dec 22, 2023Updated 2 years ago
- ☆34Feb 20, 2024Updated 2 years ago
- ☆84Feb 4, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- wifi☆12Jun 13, 2017Updated 9 years ago
- ☆29Oct 20, 2019Updated 7 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆26Mar 25, 2025Updated last year
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- General Purpose AXI Direct Memory Access☆83May 12, 2024Updated 2 years ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- ☆10Nov 2, 2023Updated 3 years ago