agalimberti / NoCRouterLinks
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
☆135Updated 7 years ago
Alternatives and similar repositories for NoCRouter
Users that are interested in NoCRouter are comparing it to the libraries listed below
Sorting:
- An AXI4 crossbar implementation in SystemVerilog☆180Updated 2 months ago
- Network on Chip Implementation written in SytemVerilog☆194Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆181Updated last year
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- A Fast, Low-Overhead On-chip Network☆239Updated last week
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆95Updated 6 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆82Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆107Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- ☆37Updated 6 years ago
- AXI总线连接器☆105Updated 5 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆191Updated 5 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- round robin arbiter☆76Updated 11 years ago
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- ☆65Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- ☆78Updated 11 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆21Updated last year
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- Some useful documents of Synopsys☆90Updated 4 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆138Updated 5 years ago
- Verilog Configurable Cache☆185Updated last week
- A collection of commonly asked RTL design interview questions☆35Updated 8 years ago
- Introductory course into static timing analysis (STA).☆99Updated 4 months ago
- ☆208Updated 8 months ago
- IEEE 754 floating point unit in Verilog☆148Updated 9 years ago
- VIP for AXI Protocol☆158Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago