maeri-project / MAERI_bsv
MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
☆59Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for MAERI_bsv
- MAERI public release☆31Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆71Updated 3 months ago
- ☆69Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- MAESTRO binary release☆22Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆63Updated 5 years ago
- ☆24Updated 7 months ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆25Updated 6 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆80Updated last month
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆46Updated 2 weeks ago
- RTL implementation of Flex-DPE.☆91Updated 4 years ago
- ☆33Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆30Updated last month
- ☆70Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆31Updated 2 years ago
- gem5 repository to study chiplet-based systems☆66Updated 5 years ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆23Updated 7 months ago
- ☆23Updated 3 years ago
- research, experimentation and implementation of hardware-agnostic accelerated DL framework☆33Updated 3 weeks ago
- A general framework for optimizing DNN dataflow on systolic array☆33Updated 3 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆126Updated 2 months ago
- An HLS based winograd systolic CNN accelerator☆48Updated 3 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆99Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆116Updated 4 years ago
- An integrated CGRA design framework☆83Updated last week
- ☆32Updated 5 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago