cameronshinn / tiny-tpuLinks
Small-scale Tensor Processing Unit built on an FPGA
☆214Updated 6 years ago
Alternatives and similar repositories for tiny-tpu
Users that are interested in tiny-tpu are comparing it to the libraries listed below
Sorting:
- IC implementation of TPU☆143Updated 6 years ago
- IC implementation of Systolic Array for TPU☆318Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆236Updated 2 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆174Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆158Updated 9 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆112Updated 5 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆168Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆166Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆198Updated 3 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆71Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆123Updated 5 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆205Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆140Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆196Updated 8 years ago
- A Fast, Low-Overhead On-chip Network☆255Updated 2 weeks ago
- AMD University Program HLS tutorial☆121Updated last year
- Verilog implementation of Softmax function☆78Updated 3 years ago
- ☆45Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆148Updated 7 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Implementation of CNN using Verilog☆233Updated 8 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- ☆123Updated 5 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆53Updated 8 years ago
- IEEE 754 floating point unit in Verilog☆150Updated 9 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆133Updated 10 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆527Updated 6 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago