Small-scale Tensor Processing Unit built on an FPGA
☆230Aug 4, 2019Updated 7 years ago
Alternatives and similar repositories for tiny-tpu
Users that are interested in tiny-tpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IC implementation of TPU☆160Dec 18, 2019Updated 6 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆579Jan 5, 2019Updated 7 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆176Jul 25, 2019Updated 7 years ago
- ☆56Jan 14, 2021Updated 5 years ago
- AI Chip project☆34Jul 14, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- IC implementation of Systolic Array for TPU☆371Oct 21, 2024Updated last year
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆780Dec 6, 2017Updated 8 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆175May 10, 2025Updated last year
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆276May 6, 2023Updated 3 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- ☆15Apr 24, 2023Updated 3 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆178Jun 9, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Systolic-array based Deep Learning Accelerator generator☆29Dec 11, 2020Updated 5 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆17May 17, 2024Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆186Dec 14, 2019Updated 6 years ago
- An AI accelerator implementation with Xilinx FPGA☆123Sep 3, 2026Updated 2 weeks ago
- Theia: ray graphic processing unit☆21Jul 17, 2014Updated 12 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆202Dec 15, 2017Updated 8 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 7 years ago
- a Computing In Memory emULATOR framework☆16May 19, 2024Updated 2 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 7 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Hardware-accelerated sorting algorithm☆16May 4, 2020Updated 6 years ago