Alternatives and similar repositories for tiny-tpu:

Users that are interested in tiny-tpu are comparing it to the libraries listed below

• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆123Updated 5 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆235Updated 6 months ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆118Updated 2 months ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆196Updated 2 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆145Updated last year
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆150Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆158Updated 5 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆147Updated last week
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆179Updated 7 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆96Updated 2 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆99Updated 4 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆84Updated 6 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆150Updated 10 months ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆110Updated 4 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆103Updated 3 years ago
• dldldlfma / super_small_toy_tpu
  ☆38Updated 4 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆53Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆72Updated last year
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆193Updated this week
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆212Updated 7 years ago
• RV-BOSC / OpenNoC
  ☆153Updated last week
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆87Updated 4 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆190Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆112Updated 10 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆174Updated 2 years ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆464Updated 6 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆66Updated 2 months ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆65Updated 2 years ago
• cxdzyq1110 / NPU_on_FPGA
  在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
  ☆237Updated 6 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆135Updated 8 years ago