ramachav / Simple-Neural-Network-Accelerator
Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerate the inference on a database of 10000 images. The trained model was made using KANN C libraries and the accelerator was synthesized as part of an SoC on an Altera FPGA.
☆9Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for Simple-Neural-Network-Accelerator
- ☆64Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- HLS implemented systolic array structure☆40Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- eyeriss-chisel3☆38Updated 2 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- ☆60Updated 5 years ago
- IC implementation of TPU☆86Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- Convolution Neural Network of vgg19 model in verilog☆43Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆48Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆27Updated last year
- Systolic-array based Deep Learning Accelerator generator☆24Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆24Updated 3 years ago
- A systolic array matrix multiplier☆23Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆166Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆35Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆82Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆30Updated last year
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆21Updated 5 years ago
- ☆69Updated 4 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆88Updated 6 years ago
- ☆76Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆51Updated 6 years ago
- CNN accelerator☆26Updated 7 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆12Updated 3 years ago