ramachav / Simple-Neural-Network-Accelerator
Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerate the inference on a database of 10000 images. The trained model was made using KANN C libraries and the accelerator was synthesized as part of an SoC on an Altera FPGA.
☆10Updated 5 years ago
Alternatives and similar repositories for Simple-Neural-Network-Accelerator:
Users that are interested in Simple-Neural-Network-Accelerator are comparing it to the libraries listed below
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- ☆64Updated 2 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- IC implementation of TPU☆97Updated 5 years ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- CNN Accelerator in Frequency Domain☆12Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- HLS for Networks-on-Chip☆33Updated 3 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- ☆60Updated 6 years ago
- CNN accelerator☆27Updated 7 years ago
- ☆33Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆139Updated 5 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆40Updated 5 months ago
- ☆24Updated 5 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 3 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆170Updated 7 years ago
- ☆100Updated 4 years ago