ramachav / Simple-Neural-Network-AcceleratorLinks
Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerate the inference on a database of 10000 images. The trained model was made using KANN C libraries and the accelerator was synthesized as part of an SoC on an Altera FPGA.
☆11Updated 5 years ago
Alternatives and similar repositories for Simple-Neural-Network-Accelerator
Users that are interested in Simple-Neural-Network-Accelerator are comparing it to the libraries listed below
Sorting:
- ☆66Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆197Updated 5 years ago
- IC implementation of TPU☆127Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆188Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆105Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- ☆65Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 5 years ago
- ☆113Updated 4 years ago
- Verilog implementation of Softmax function☆67Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- Library of approximate arithmetic circuits☆55Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- FFT generator using Chisel☆61Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆40Updated 5 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆34Updated 4 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆78Updated 7 years ago