Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerate the inference on a database of 10000 images. The trained model was made using KANN C libraries and the accelerator was synthesized as part of an SoC on an Altera FPGA.
☆11Dec 13, 2019Updated 6 years ago
Alternatives and similar repositories for Simple-Neural-Network-Accelerator
Users that are interested in Simple-Neural-Network-Accelerator are comparing it to the libraries listed below
Sorting:
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- ☆13Aug 21, 2019Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Oct 6, 2019Updated 6 years ago
- ☆27Apr 28, 2020Updated 5 years ago
- DAG-based blockchain☆10Apr 20, 2019Updated 6 years ago
- ☆36Jan 27, 2018Updated 8 years ago
- Kernel module that makes it possible to create virtual wifi devices each with a virtualized stack.☆11Dec 13, 2011Updated 14 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- This is a hanabi AI bot that can play on http://keldon.net/hanabi/☆11May 29, 2017Updated 8 years ago
- ☆13Jan 17, 2022Updated 4 years ago
- Gesture Recognition Based on ALTERA DE2-115 FPGA☆10Mar 18, 2014Updated 11 years ago
- Embed the Power of Lua into NGINX HTTP servers☆11Dec 1, 2015Updated 10 years ago
- BlockCIrculantRNN (LSTM and GRU) using TensorFlow☆14Oct 30, 2018Updated 7 years ago
- Free TPU OS running on the FPGA☆10May 6, 2023Updated 2 years ago
- Minimal ZX Spectrum for Ulx3s ECP5 board☆12May 7, 2020Updated 5 years ago
- BabbleSim base/common components. Any BabbleSim user will want some of these.☆17Feb 23, 2026Updated last week
- GUI for SymbiYosys☆17Oct 13, 2025Updated 4 months ago
- MetroHash v1: Exceptionally fast and statistically robust hash functions☆10Apr 10, 2025Updated 10 months ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆10Nov 16, 2024Updated last year
- internship☆10Sep 1, 2017Updated 8 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- BOSSA is the programming software used to program SAM-based Arduino boards like Flutter. We added our chip.☆12Mar 17, 2015Updated 10 years ago
- Tiny C library for inter-thread/process communication via channels. Linux-only.☆12Feb 21, 2016Updated 10 years ago
- Python client for Perforce Helix Swarm☆10Sep 11, 2024Updated last year
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- Huffman encoder☆10Sep 8, 2013Updated 12 years ago
- Unreal Engine simulator for our self driving car training☆11Nov 18, 2021Updated 4 years ago
- biRISC-V - 32-bit dual issue RISC-V CPU Software Environment☆15Jun 24, 2021Updated 4 years ago
- ☆10Jun 28, 2019Updated 6 years ago
- ☆13Feb 13, 2026Updated 2 weeks ago
- PID control library for Particle, adapted from br3ttb/Arduino-PID-Library☆11Feb 15, 2024Updated 2 years ago
- `async-ctrlc` is an async wrapper of the `ctrlc` crate in Rust☆15May 30, 2020Updated 5 years ago
- Fast Setup for Proof by Reflection, in Two Lines of Ltac.☆14Jan 12, 2021Updated 5 years ago
- research, experimentation and implementation of hardware-agnostic accelerated DL framework☆39Aug 31, 2025Updated 6 months ago