Alternatives and similar repositories for MPSoC-NoC

Users that are interested in MPSoC-NoC are comparing it to the libraries listed below

• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated last week
• pulp-platform / hier-icache
  ☆14Updated 10 months ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆30Updated 3 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆32Updated 7 years ago
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• pulp-platform / axi_llc
  ☆33Updated last month
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆27Updated 6 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆34Updated 9 years ago
• pulp-platform / apb
  APB Logic
  ☆22Updated 2 months ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated last week
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆32Updated last week
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆36Updated 8 months ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆17Updated 4 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• pulp-platform / ace
  ☆20Updated 3 weeks ago
• jiayi-wang98 / lpddr4_memory_controller
  ☆10Updated 3 years ago
• frobino / Nostrum-SystemC-simulator
  SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
  ☆14Updated 11 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 11 months ago
• PacoReinaCampo / MPSoC-RISCV
  Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆13Updated last week
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆15Updated 8 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year