ucb-bar / gemminiLinks
Berkeley's Spatial Array Generator
☆1,007Updated 3 months ago
Alternatives and similar repositories for gemmini
Users that are interested in gemmini are comparing it to the libraries listed below
Sorting:
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,915Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆776Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆448Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,052Updated 10 months ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆487Updated 6 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆426Updated 5 years ago
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆477Updated last year
- Digital Design with Chisel☆852Updated last month
- Open, Modular, Deep Learning Accelerator☆298Updated last year
- chisel tutorial exercises and answers☆736Updated 3 years ago
- Repository to host and maintain scale-sim-v2 code☆321Updated 3 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆505Updated 8 months ago
- RTL, Cmodel, and testbench for NVDLA☆1,916Updated 3 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆381Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆516Updated 5 months ago
- A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …☆643Updated last year
- A template project for beginning new Chisel work☆655Updated 2 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆586Updated 11 months ago
- synthesiseable ieee 754 floating point library in verilog☆661Updated 2 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆352Updated 6 months ago
- ☆334Updated 10 months ago
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆410Updated last week
- ☆635Updated 4 years ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆385Updated last year
- IC implementation of Systolic Array for TPU☆263Updated 9 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆948Updated last month
- Flexible Intermediate Representation for RTL☆747Updated 11 months ago
- Vitis_Accel_Examples☆553Updated last month
- Network on Chip Simulator☆283Updated 2 weeks ago
- Documentation for NVDLA.☆250Updated last week