Berkeley's Spatial Array Generator
☆1,251Mar 19, 2026Updated this week
Alternatives and similar repositories for gemmini
Users that are interested in gemmini are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,183Updated this week
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆464Feb 19, 2026Updated last month
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆63Jun 27, 2025Updated 8 months ago
- Repository to host and maintain SCALE-Sim code☆436Feb 2, 2026Updated last month
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…☆2,070Nov 8, 2025Updated 4 months ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆159May 26, 2025Updated 9 months ago
- Rocket Chip Generator☆3,722Feb 25, 2026Updated 3 weeks ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆92Mar 26, 2023Updated 2 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,003Mar 9, 2026Updated last week
- Open, Modular, Deep Learning Accelerator☆334Apr 10, 2024Updated last year
- RTL, Cmodel, and testbench for NVDLA☆2,031Mar 2, 2022Updated 4 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆257Oct 6, 2022Updated 3 years ago
- Chisel: A Modern Hardware Design Language☆4,611Updated this week
- ☆661Jan 13, 2021Updated 5 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆878Mar 16, 2026Updated last week
- ☆368Sep 12, 2025Updated 6 months ago
- Digital Design with Chisel☆899Mar 13, 2026Updated last week
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆191Jan 8, 2026Updated 2 months ago
- ☆377May 11, 2023Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 4 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆149Jun 16, 2025Updated 9 months ago
- Circuit IR Compilers and Tools☆2,065Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,121Sep 10, 2024Updated last year
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Dec 22, 2025Updated 3 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆500Mar 14, 2026Updated last week
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆247Apr 15, 2024Updated last year
- ☆1,939Updated this week
- RTL implementation of Flex-DPE.☆115Feb 22, 2020Updated 6 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆114Jan 4, 2023Updated 3 years ago
- A template project for beginning new Chisel work☆695Feb 24, 2026Updated 3 weeks ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆445Dec 2, 2019Updated 6 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆240Dec 8, 2022Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,851Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆164Jan 25, 2024Updated 2 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆406Updated this week
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆125Aug 27, 2024Updated last year