Alternatives and similar repositories for dac_sdc_2021:

Users that are interested in dac_sdc_2021 are comparing it to the libraries listed below

• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆36Updated 4 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆23Updated 2 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆34Updated 4 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• GATECH-EIC / Auto-NBA
  [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…
  ☆15Updated 3 years ago
• PSCLab-ASU / Systolic-CNN
  ☆15Updated 4 years ago
• hqjenny / CoDeNet
  ☆19Updated 4 years ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆17Updated 5 years ago
• heymesut / SJTU_microe
  A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
  ☆28Updated 2 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆50Updated 2 weeks ago
• fffasttime / AnyPackingNet
  ☆26Updated 3 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 3 weeks ago
• AiArtisan / dac_sdc_2022_champion
  ☆21Updated 2 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆31Updated 5 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 5 years ago
• xyzxinyizhang / 2019-DAC-System-Design-Contest
  ☆35Updated 5 years ago
• CASR-HKU / DPACS
  ☆19Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆25Updated 4 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆37Updated 2 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆57Updated 3 years ago
• xliu0709 / DACSDC2021
  ☆11Updated 11 months ago
• nimish15shah / DAG_Processor
  A DAG processor and compiler for a tree-based spatial datapath.
  ☆13Updated 2 years ago
• ZhangYuQAQ / Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA
  2020 xilinx summer school
  ☆17Updated 4 years ago