xjtuiair-cag / XJTU-Tripler
XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
☆175Updated last year
Alternatives and similar repositories for XJTU-Tripler:
Users that are interested in XJTU-Tripler are comparing it to the libraries listed below
- The second place winner for DAC-SDC 2020☆97Updated 2 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆111Updated 4 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆143Updated 5 years ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆304Updated 4 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆226Updated 6 years ago
- ☆238Updated 2 years ago
- 中文：☆97Updated 5 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆89Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 6 years ago
- ☆33Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆177Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆109Updated 7 years ago
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆140Updated 7 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆63Updated 5 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 5 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆236Updated 3 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 2 months ago
- 2019 SEU-Xilinx Summer School☆48Updated 5 years ago
- ☆44Updated 6 years ago
- An LeNet RTL implement onto FPGA☆44Updated 6 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆330Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆99Updated 6 years ago
- DPU on PYNQ☆211Updated last year
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆209Updated 5 years ago
- Residual Binarized Neural Network☆43Updated 6 years ago