jiangwx / SkrSkrLinks
The second place winner for DAC-SDC 2020
☆97Updated 3 years ago
Alternatives and similar repositories for SkrSkr
Users that are interested in SkrSkr are comparing it to the libraries listed below
Sorting:
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆90Updated 6 years ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 5 months ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 5 years ago
- ☆11Updated last year
- hls code zynq 7020 pynq z2 CNN☆84Updated 6 years ago
- ☆26Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 4 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- 中文:☆101Updated 5 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆186Updated 7 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- The CNN based on the Xilinx Vivado HLS☆36Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆155Updated 5 years ago
- ☆112Updated 4 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- ☆33Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆102Updated 6 years ago
- ☆46Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.☆182Updated last year
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago