CASR-HKU / MSD-FCCM23Links
Open-source of MSD framework
☆16Updated 2 years ago
Alternatives and similar repositories for MSD-FCCM23
Users that are interested in MSD-FCCM23 are comparing it to the libraries listed below
Sorting:
- ☆28Updated 5 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- ☆18Updated 2 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- ☆44Updated 2 years ago
- C++ code for HLS FPGA implementation of transformer☆18Updated last year
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆87Updated 7 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago
- A collection of tutorials for the fpgaConvNet framework.☆45Updated 11 months ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated 3 weeks ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- Collection of kernel accelerators optimised for LLM execution☆21Updated 5 months ago
- ☆14Updated 3 years ago
- ☆17Updated 4 months ago
- ☆11Updated last year
- ☆21Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆33Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- Model LLM inference on single-core dataflow accelerators☆14Updated last month
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆18Updated 6 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆116Updated 5 years ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- ☆34Updated 6 years ago
- A co-design architecture on sparse attention☆51Updated 4 years ago