Alternatives and similar repositories for MSD-FCCM23

Users that are interested in MSD-FCCM23 are comparing it to the libraries listed below

• fffasttime / AnyPackingNet
  ☆27Updated 2 months ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆43Updated last year
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• CASR-HKU / AGNA-FCCM2023
  ☆12Updated last year
• RakeshUIUC / multihead_attn_accelerator
  Accelerate multihead attention transformer model using HLS for FPGA
  ☆11Updated last year
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆56Updated 4 months ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated 10 months ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆52Updated 3 years ago
• mustard-seed / SparseDNNAccelerator
  Sparse CNN Accelerator targeting Intel FPGA
  ☆11Updated 3 years ago
• albertomarchisio / SwiftTron
  ☆44Updated 2 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆17Updated 8 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆53Updated last month
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• isakedo / DNNsim
  ☆34Updated 4 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆82Updated 3 years ago
• gl9544 / vit_transformer_fpga
  ☆15Updated last year
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆39Updated 8 months ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆43Updated 2 years ago
• heymesut / SJTU_microe
  A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
  ☆28Updated 3 years ago
• gem5-X / TiC-SAT
  ☆16Updated 3 weeks ago
• xliu0709 / DACSDC2021
  ☆11Updated last year
• abdelfattah-lab / BRAMAC
  ☆10Updated 6 months ago
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆10Updated 3 months ago
• ECASLab / hls-fpga-accelerators
  Collection of kernel accelerators optimised for LLM execution
  ☆17Updated 2 months ago
• hyupupup / conv_systolic_array
  (Verilog) A simple convolution layer implementation with systolic array structure
  ☆13Updated 3 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆16Updated 6 years ago