Open-source of MSD framework
☆16Sep 12, 2023Updated 3 years ago
Alternatives and similar repositories for MSD-FCCM23
Users that are interested in MSD-FCCM23 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆12Nov 24, 2023Updated 2 years ago
- ☆20Mar 21, 2023Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆21Jul 9, 2024Updated 2 years ago
- An FPGA Accelerator for Transformer Inference☆98Apr 29, 2022Updated 4 years ago
- ☆20Mar 16, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆23Oct 26, 2022Updated 3 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- Reconfigurable Stream Network Architecture☆18Aug 13, 2026Updated 2 months ago
- ☆11Oct 27, 2022Updated 3 years ago
- An open-sourced PyTorch library for developing energy efficient multiplication-less models and applications.☆14Feb 3, 2025Updated last year
- ☆35Mar 1, 2019Updated 7 years ago
- ☆32Mar 31, 2025Updated last year
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆144May 10, 2024Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆20Aug 14, 2026Updated 2 months ago
- Codes for our paper "Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment" [NeurIPS'19 EMC2 workshop]…☆10Oct 12, 2020Updated 6 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆107Sep 27, 2024Updated 2 years ago
- ☆24May 14, 2025Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆48Aug 8, 2022Updated 4 years ago
- ☆19Nov 11, 2024Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆85Nov 7, 2021Updated 4 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Aug 28, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- STONNE Simulator integrated into SST Simulator☆22Apr 5, 2024Updated 2 years ago
- PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow☆69May 9, 2023Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆29May 18, 2025Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆38Mar 12, 2026Updated 7 months ago
- training SNN with Resume algorithm☆10Nov 15, 2019Updated 6 years ago
- ☆24Sep 17, 2024Updated 2 years ago
- Unit Scaling demo and experimentation code☆15Mar 12, 2024Updated 2 years ago
- ☆19Jan 8, 2026Updated 9 months ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆56Mar 24, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Revisit Kernel Pruning with Lottery Regulated Grouped Convolutions. ICLR 2022☆11Nov 24, 2022Updated 3 years ago
- ☆73Feb 16, 2023Updated 3 years ago
- nn2FPGA converts ONNX models into FPGA dataflow accelerators with seamless ONNX Runtime integration.☆25Sep 15, 2026Updated last month
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- Performs a faster tensor train (TT) decomposition for large sparse data☆14Sep 7, 2020Updated 6 years ago
- RedEye is a vision sensor designed to execute early stages of a deep convolutional neural network (ConvNet) in the analog domain. This re…☆14Dec 16, 2016Updated 9 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆178Mar 12, 2026Updated 7 months ago