xyzxinyizhang / 2019-DAC-System-Design-ContestView external linksLinks
☆35Jul 24, 2019Updated 6 years ago
Alternatives and similar repositories for 2019-DAC-System-Design-Contest
Users that are interested in 2019-DAC-System-Design-Contest are comparing it to the libraries listed below
Sorting:
- ☆53Jul 24, 2019Updated 6 years ago
- DAC System Design Contest 2020☆29Jun 11, 2020Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Jul 8, 2020Updated 5 years ago
- ☆243Jun 21, 2022Updated 3 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆91Nov 25, 2018Updated 7 years ago
- ☆23Oct 7, 2021Updated 4 years ago
- The second place winner for DAC-SDC 2020☆99Apr 23, 2022Updated 3 years ago
- ☆19Mar 16, 2022Updated 3 years ago
- ☆28Nov 5, 2021Updated 4 years ago
- a project build the SSD net in pynq-z2☆15Aug 1, 2020Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆92May 25, 2019Updated 6 years ago
- XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.☆194Jan 10, 2024Updated 2 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆114Feb 22, 2021Updated 4 years ago
- ☆47Nov 23, 2023Updated 2 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18May 12, 2022Updated 3 years ago
- ☆16Jul 13, 2018Updated 7 years ago
- ☆19Mar 17, 2021Updated 4 years ago
- Lecture Material on Deep Learning Inference using FPGA☆12Jun 9, 2020Updated 5 years ago
- A unified programming framework for high and portable performance across FPGAs and GPUs☆11Mar 23, 2025Updated 10 months ago
- ☆72Feb 16, 2023Updated 3 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- Diving Deeper into Underwater Image Enhancement: A Survey, accepted in Signal Processing: Image Communication.☆11Aug 9, 2020Updated 5 years ago
- ☆26Nov 4, 2022Updated 3 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28May 11, 2022Updated 3 years ago
- Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices☆12Jul 1, 2021Updated 4 years ago
- [CVPR 2022] DiSparse: Disentangled Sparsification for Multitask Model Compression☆14Sep 6, 2022Updated 3 years ago
- Yolov4-tiny and Yolo-Fastest (Tensorflow2) is used to detect vehicles on Ultra96-v2 board, and we support model pruning.☆32Jan 26, 2021Updated 5 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Nov 15, 2022Updated 3 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆282Dec 5, 2019Updated 6 years ago
- ☆13Jul 14, 2020Updated 5 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆241Apr 12, 2021Updated 4 years ago
- Open Source Projects from Pallas Lab☆20Oct 10, 2021Updated 4 years ago
- ☆17Nov 20, 2022Updated 3 years ago
- Model deployment, Yolov4, xilinx, Ultra96_v2.☆15Nov 4, 2021Updated 4 years ago
- ☆43Jan 30, 2024Updated 2 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 5 years ago
- Board files to build Ultra 96 PYNQ image☆157Sep 14, 2025Updated 5 months ago