Alternatives and similar repositories for Open-Source-IPs

Users that are interested in Open-Source-IPs are comparing it to the libraries listed below

• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 5 months ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆53Updated 4 years ago
• fffasttime / AnyPackingNet
  ☆28Updated 4 months ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 5 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆46Updated 3 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 2 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆94Updated 3 years ago
• gicLAB / SECDA
  ☆25Updated 2 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆32Updated 6 years ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆58Updated 3 years ago
• PSCLab-ASU / Systolic-CNN
  ☆16Updated 4 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆57Updated last month
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆45Updated last year
• sharc-lab / FPGA_ECE8893
  ☆36Updated 4 months ago
• gem5-X / TiC-SAT
  ☆17Updated 2 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆107Updated 5 years ago