Alternatives and similar repositories for dac_sdc_2020_designs

Users that are interested in dac_sdc_2020_designs are comparing it to the libraries listed below

• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 5 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆53Updated 3 years ago
• AiArtisan / dac_sdc_2022_champion
  ☆21Updated 2 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆113Updated 4 years ago
• heymesut / SJTU_microe
  A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
  ☆28Updated 3 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• jgoeders / dac_sdc_2022_designs
  ☆17Updated 2 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆39Updated 4 years ago
• fffasttime / AnyPackingNet
  ☆27Updated 3 months ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆94Updated 3 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 2 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆42Updated 9 months ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 6 years ago
• PSCLab-ASU / Systolic-CNN
  ☆16Updated 4 years ago
• ZhangYuQAQ / Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA
  2020 xilinx summer school
  ☆17Updated 4 years ago
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆97Updated 3 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆37Updated 4 years ago
• hqjenny / CoDeNet
  ☆19Updated 4 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆80Updated 11 months ago
• sharc-lab / FPGA_ECE8893
  ☆35Updated 3 months ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago