louisliuwei / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLSLinks
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆38Updated 5 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- 2019 SEU-Xilinx Summer School☆50Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆38Updated 5 years ago
- hls code zynq 7020 pynq z2 CNN☆85Updated 6 years ago
- ☆46Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆103Updated 6 years ago
- 中文:☆101Updated 5 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 7 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆72Updated 6 years ago
- ☆65Updated 6 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆153Updated 5 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- ☆89Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 6 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆51Updated 7 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆33Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago