louisliuwei / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLSLinks
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆38Updated 6 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- 2019 SEU-Xilinx Summer School☆50Updated 6 years ago
- PYNQ学习资料☆174Updated 6 years ago
- 中文:☆108Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆89Updated 6 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆241Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆51Updated 5 years ago
- The second place winner for DAC-SDC 2020☆99Updated 3 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆114Updated 4 years ago
- ☆48Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆115Updated 8 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- An LeNet RTL implement onto FPGA☆51Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆74Updated 7 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆167Updated 6 years ago
- This project is trying to create a base vitis platform to run with DPU☆49Updated 5 years ago
- XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.☆193Updated 2 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆41Updated 5 years ago
- ☆72Updated 7 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆92Updated 6 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆104Updated 2 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆196Updated 8 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆194Updated last year
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆186Updated 8 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- DPU on PYNQ☆237Updated 5 months ago