louisliuwei / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆38Updated 5 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS:
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below
- 2019 SEU-Xilinx Summer School☆48Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 5 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆108Updated 7 years ago
- PYNQ学习资料☆160Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆94Updated 6 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆235Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆62Updated 6 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆15Updated 6 years ago
- 中文:☆95Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- 3×3脉动阵列乘法器☆38Updated 5 years ago
- FFT generator using Chisel☆57Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆63Updated last month
- An LeNet RTL implement onto FPGA☆40Updated 6 years ago
- ☆87Updated 4 years ago
- The second place winner for DAC-SDC 2020☆97Updated 2 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆167Updated 11 months ago
- ☆43Updated 6 years ago
- ☆60Updated 6 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆173Updated 7 years ago