This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆39Nov 25, 2019Updated 6 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 2019 SEU-Xilinx Summer School☆50Jul 26, 2019Updated 7 years ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆42Oct 15, 2019Updated 6 years ago
- The second place winner for DAC-SDC 2020☆101Apr 23, 2022Updated 4 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆118Feb 22, 2021Updated 5 years ago
- PYNQ学习资料☆178Nov 28, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆19Jul 19, 2018Updated 8 years ago
- Open source FPGA-based NIC and platform for in-network compute☆18May 22, 2024Updated 2 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆158Jan 23, 2020Updated 6 years ago
- "mmult" example using SDSoC for PYNQ board☆11Feb 23, 2017Updated 9 years ago
- view at https://xupsh.github.io/ccc2021/☆23Apr 16, 2022Updated 4 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆244Apr 12, 2021Updated 5 years ago
- https://www.hackster.io/Altaga/facemask-detector-f0c10f☆14Jan 6, 2023Updated 3 years ago
- Python HPGL parsing library☆21Nov 25, 2020Updated 5 years ago
- 中文版 Parallel Programming for FPGAs☆772Aug 21, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Apr 13, 2018Updated 8 years ago
- FPGA Accelerator for CNN using Vivado HLS☆340Oct 25, 2021Updated 4 years ago
- Python Productivity for ZYNQ☆2,341Updated this week
- Programmatically control ROS Bag files.☆13Sep 5, 2017Updated 8 years ago
- ☆14Dec 22, 2024Updated last year
- BiSUNA framework specialized to compile for the Xilinx Alveo U50☆13Dec 3, 2020Updated 5 years ago
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- An accelerator for high-dimensional approximate nearest neighbor search☆15May 17, 2025Updated last year
- ☆805Jul 13, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆12Aug 12, 2020Updated 6 years ago
- 프론트 개발자 여자친구의 특별한 생일 이벤트 프로젝트 🎉☆10Oct 23, 2023Updated 2 years ago
- ☆15Feb 25, 2017Updated 9 years ago
- ☆92Apr 15, 2020Updated 6 years ago
- ☆13Oct 8, 2024Updated last year
- Memory Benchmark for OpenCL-supported Intel FPGAs☆12Dec 25, 2023Updated 2 years ago
- Ultra96 PYNQ入门之一次简单的总结☆14May 21, 2020Updated 6 years ago
- Convert AEDAT4 files from DV into AEDAT-2.0 files for jAER☆10Feb 23, 2024Updated 2 years ago
- 精选了一系列很棒的学习或者练习算法的网址、项目等,受到 awesome-awesomeness 以及其他 awesome 系列项目的启发。☆20Jun 6, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆19Dec 20, 2023Updated 2 years ago
- it is a set for all the respository of the project.☆100Jul 23, 2019Updated 7 years ago
- Accelerate convolution neural network for face recognition using GPU☆15Nov 24, 2020Updated 5 years ago
- ☆22Dec 3, 2025Updated 8 months ago
- ☆11Sep 9, 2022Updated 3 years ago
- Verilog for ASIC Design☆35Sep 13, 2021Updated 4 years ago
- Verilog implementation of Mersenne Twister PRNG☆31Jun 20, 2018Updated 8 years ago