louisliuwei / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLSLinks
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
☆38Updated 5 years ago
Alternatives and similar repositories for High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
Users that are interested in High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS are comparing it to the libraries listed below
Sorting:
- 2019 SEU-Xilinx Summer School☆49Updated 5 years ago
- PYNQ学习资料☆164Updated 5 years ago
- hls code zynq 7020 pynq z2 CNN☆83Updated 6 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆237Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- 中文:☆101Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- ☆47Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- FPGA Accelerator for CNN using Vivado HLS☆317Updated 3 years ago
- FPGA/AES/LeNet/VGG16☆105Updated 6 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆96Updated last year
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆46Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆72Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆182Updated 8 years ago
- ☆65Updated 6 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆183Updated last year
- This project is trying to create a base vitis platform to run with DPU☆47Updated 5 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 6 years ago
- FPGA implementation of Cellular Neural Network (CNN)☆142Updated 7 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago