Inference-and-Optimization / High-Level-Synthesis-Study-NotesLinks
Vivado HLS study notes, courses, documents.
☆12Updated 6 years ago
Alternatives and similar repositories for High-Level-Synthesis-Study-Notes
Users that are interested in High-Level-Synthesis-Study-Notes are comparing it to the libraries listed below
Sorting:
- Accelerate multihead attention transformer model using HLS for FPGA☆11Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆36Updated 3 years ago
- ☆45Updated this week
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- A list of our chiplet simulaters☆47Updated 7 months ago
- ☆56Updated 2 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆56Updated 2 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆86Updated 5 months ago
- An FPGA Accelerator for Transformer Inference☆93Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆75Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆43Updated 4 years ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆46Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated last week
- eyeriss-chisel3☆40Updated 3 years ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆22Updated 10 months ago
- Attentionlego☆12Updated 2 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆30Updated 2 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆85Updated 9 months ago
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- ☆36Updated last year
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆21Updated 6 years ago
- An integrated CGRA design framework☆91Updated 10 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- RTL generator for SpGEMM☆10Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago