heymesut / SJTU_microeLinks
A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
☆28Updated 3 years ago
Alternatives and similar repositories for SJTU_microe
Users that are interested in SJTU_microe are comparing it to the libraries listed below
Sorting:
- ☆21Updated 2 years ago
- ☆20Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆17Updated 2 years ago
- ☆26Updated 2 years ago
- ☆28Updated 4 months ago
- DAC System Design Contest 2020☆29Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- Open-source of MSD framework☆16Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆71Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- ☆11Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 3 years ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆43Updated 10 months ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆12Updated 3 years ago
- ☆23Updated 3 years ago
- ☆19Updated 4 years ago
- ☆34Updated 6 years ago
- My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …☆52Updated 2 years ago
- ☆18Updated 2 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago