grebe / ofdmLinks
Chisel Things for OFDM
☆32Updated 4 years ago
Alternatives and similar repositories for ofdm
Users that are interested in ofdm are comparing it to the libraries listed below
Sorting:
- Advanced Debug Interface☆15Updated 5 months ago
- ☆26Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- ☆59Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated 3 weeks ago
- Chisel Cheatsheet☆33Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- ☆20Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Network on Chip for MPSoC☆26Updated 3 weeks ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- Craft 2 top-level repository☆14Updated 6 years ago
- Platform Level Interrupt Controller☆41Updated last year
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- ☆29Updated 4 years ago
- ☆30Updated 2 months ago
- Docker Development Environment for SpinalHDL☆20Updated 10 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 11 months ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago