grebe / ofdmLinks
Chisel Things for OFDM
☆32Updated 5 years ago
Alternatives and similar repositories for ofdm
Users that are interested in ofdm are comparing it to the libraries listed below
Sorting:
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- Advanced Debug Interface☆14Updated 9 months ago
- Fork of OpenCores jpegencode with Cocotb testbench☆47Updated 10 years ago
- Craft 2 top-level repository☆14Updated 6 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- ☆20Updated 5 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 2 weeks ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Useful utilities for BAR projects☆32Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- ☆27Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆14Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 10 months ago