grebe / ofdm
Chisel Things for OFDM
☆30Updated 4 years ago
Related projects: ⓘ
- For contributions of Chisel IP to the chisel community.☆55Updated 7 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆29Updated 3 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆12Updated 3 years ago
- Chisel Cheatsheet☆31Updated last year
- ☆24Updated last year
- Docker Development Environment for SpinalHDL☆18Updated last month
- Advanced Debug Interface☆12Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆28Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- Extensible FPGA control platform☆52Updated last year
- Craft 2 top-level repository☆13Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆11Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 2 months ago
- ☆17Updated last week
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆32Updated 6 years ago
- LIS Network-on-Chip Implementation☆28Updated 8 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- ☆25Updated last year
- Open FPGA Modules☆22Updated last week
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆17Updated 6 years ago
- ☆19Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 2 months ago
- ☆21Updated 3 years ago
- The sources of the online SpinalHDL doc☆23Updated last month
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆9Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆15Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆39Updated 3 years ago