RISC-V 32-bit core for MCCI Catena 4710
☆10Jul 31, 2019Updated 7 years ago
Alternatives and similar repositories for catena-riscv32-fpga
Users that are interested in catena-riscv32-fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 7 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- USB Full-Speed core written in migen/LiteX☆17Sep 2, 2019Updated 7 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The Micro Python project☆15Dec 24, 2020Updated 5 years ago
- Verilog Examples and WebFPGA Standard Library☆11Nov 25, 2019Updated 6 years ago
- photonSDI - an open source SDI core☆11May 26, 2021Updated 5 years ago
- AXI4 to SRAM Interface☆13May 2, 2022Updated 4 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 8 years ago
- GCC port rewrite for OpenRISC☆13May 28, 2025Updated last year
- Protoboard cartridge for the Hackaday 2019 Supercon badge☆17Nov 12, 2019Updated 6 years ago
- I2C driver (bare metal) for Freescale Kinetis microcontrollers, uses the Bus Pirate convention. ➡️☆10Feb 10, 2021Updated 5 years ago
- a C implementation of Simon Cooke's bipbuffer☆19Aug 11, 2017Updated 9 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ice40 USB Analyzer☆57Aug 8, 2020Updated 6 years ago
- chipy hdl☆17Apr 5, 2018Updated 8 years ago
- 360nosc0pe Yocto build environment☆13Aug 27, 2018Updated 8 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- Industry standard I/O for nMigen☆12Apr 23, 2020Updated 6 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Icarus SIMBUS☆21Nov 6, 2019Updated 6 years ago
- ☆17Jun 5, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- wavedrom to verilog converter☆18Sep 14, 2021Updated 5 years ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆15Sep 21, 2026Updated last month
- Where Arty S7 projects are kept. MIT License unless file headers state otherwise.☆24Sep 26, 2019Updated 7 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Sep 24, 2026Updated last month
- Contains commonly used UVM components (agents, environments and tests).☆33Aug 17, 2018Updated 8 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 7 years ago
- SPI flash MITM and emulation (QSPI is a WIP)☆22Jan 27, 2022Updated 4 years ago
- ☆15Oct 24, 2019Updated 7 years ago
- standalone python host-side module to talk to OpenVizsla devices, based on LibOV [archived]☆18Feb 1, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- HDL tools layer for OpenEmbedded☆18Oct 20, 2024Updated 2 years ago
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- Notes on/tools for/new firmware for (?) a PDC002 USB PD cable☆17Apr 8, 2021Updated 5 years ago
- A bit-serial CPU☆20Sep 29, 2019Updated 7 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 8 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago
- OSHPark 3D PCB layer visualizer based on three.js☆16Oct 6, 2018Updated 8 years ago