mcci-catena / catena-riscv32-fpgaLinks
RISC-V 32-bit core for MCCI Catena 4710
☆10Updated 6 years ago
Alternatives and similar repositories for catena-riscv32-fpga
Users that are interested in catena-riscv32-fpga are comparing it to the libraries listed below
Sorting:
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 7 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated last year
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- ☆20Updated 3 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 4 years ago
- A CIC filter implemented in Verilog☆22Updated 10 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 3 months ago
- Fork of OpenCores jpegencode with Cocotb testbench☆47Updated 10 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- LMAC Core1 - Ethernet 1G/100M/10M☆18Updated 2 years ago
- Wishbone interconnect utilities☆41Updated 8 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Updated 6 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensour…☆17Updated last month
- ☆42Updated 5 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆35Updated 4 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- An open-source VHDL library for FPGA design.☆31Updated 3 years ago
- The first-ever opensource RTL stack for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With sta…☆22Updated this week
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- Time to Digital Converter (TDC)☆35Updated 4 years ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 7 years ago