SmartNIC
☆14Dec 13, 2018Updated 7 years ago
Alternatives and similar repositories for fa18-smartnic
Users that are interested in fa18-smartnic are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chisel Things for OFDM☆33Jul 1, 2020Updated 5 years ago
- A Programmable Hardware Architecture for Network Transport Logic☆37Oct 26, 2021Updated 4 years ago
- ☆11Aug 4, 2022Updated 3 years ago
- An Agile Chisel-Based SoC Design Framework☆26Dec 29, 2021Updated 4 years ago
- ☆27Jul 27, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- LibOCXL is an access library which allows the user to implement a userspace driver for an OpenCAPI accelerator.☆13Jul 1, 2024Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Jan 6, 2022Updated 4 years ago
- LTE/WiFi/5G-NR SDR Transceiver☆56Dec 18, 2018Updated 7 years ago
- A Fast, Scalable and Programmable Packet Scheduler in Hardware☆37Jul 2, 2019Updated 6 years ago
- μP4: A framework for programming dataplane of network devices☆35Aug 4, 2020Updated 5 years ago
- ☆18Dec 11, 2023Updated 2 years ago
- Decision Trees Inference☆15Apr 25, 2018Updated 8 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- A Programmer Guide of the P4 Language.☆41Jun 4, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- ☆11Apr 3, 2023Updated 3 years ago
- HW/SW co-designed end-host RPC stack☆20Oct 28, 2021Updated 4 years ago
- Heterogeneous simulator for DECADES Project☆32May 23, 2024Updated 2 years ago
- Virtual I/O acceleration technologies for KVM☆15Sep 17, 2013Updated 12 years ago
- LeapIO: Efficient and Portable Virtual NVMe Storage on ARM SoCs (ASPLOS'20)☆30Oct 3, 2021Updated 4 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆30Jan 25, 2024Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆33Nov 13, 2023Updated 2 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 5 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆236Dec 22, 2025Updated 5 months ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆89Mar 17, 2026Updated 3 months ago
- Compression for Foundation Models☆36Jul 21, 2025Updated 10 months ago
- The accelerometer analytical model published in ASPLOS 2020 (Accelerometer: Understanding Acceleration Opportunities forData Center Overh…☆16Jan 18, 2020Updated 6 years ago
- Rcmp: Reconstructing RDMA-based Memory Disaggregation via CXL☆64Dec 26, 2023Updated 2 years ago
- A library for PCIe Transaction Layer☆62Apr 27, 2022Updated 4 years ago
- Multi-platform topology-aware memory management library☆12Apr 23, 2020Updated 6 years ago
- FeRTOS is a simple "operating system" that currently supports ARM Cortex-M CPUs☆12Jul 9, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Dynamic types for OCaml☆24Feb 15, 2016Updated 10 years ago
- git://gitorious.org/flashimg/flashimg.git☆13Nov 25, 2013Updated 12 years ago
- A datacenter network framework that aims for high utilization with zero queueing. A logically centralized arbiter controls and orchestrat…☆159Oct 11, 2016Updated 9 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆33Oct 15, 2024Updated last year
- ☆14Sep 27, 2021Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago