ucb-ee290c / fa18-smartnicLinks
SmartNIC
☆14Updated 6 years ago
Alternatives and similar repositories for fa18-smartnic
Users that are interested in fa18-smartnic are comparing it to the libraries listed below
Sorting:
- P4 compatible HLS modules☆11Updated 7 years ago
- ☆35Updated 4 years ago
- Networking Template Library for Vivado HLS☆28Updated 5 years ago
- An FPGA-based NetTLP adapter☆26Updated 5 years ago
- corundum work on vu13p☆19Updated last year
- Tutorial Material from the SST Team☆21Updated 3 weeks ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago
- A parallel and distributed simulator for thousand-core chips☆25Updated 7 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆38Updated 7 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 3 weeks ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- ☆10Updated 2 years ago
- ☆34Updated 9 years ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆37Updated 5 months ago
- ☆19Updated 4 years ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆103Updated 2 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- Caribou: Distributed Smart Storage built with FPGAs☆67Updated 7 years ago
- FPGA-based HyperLogLog Accelerator☆12Updated 5 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- ☆13Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- An Agile Chisel-Based SoC Design Framework☆26Updated 3 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆46Updated last week
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated this week
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 7 months ago