ucb-ee290c / fa18-smartnicLinks
SmartNIC
☆14Updated 6 years ago
Alternatives and similar repositories for fa18-smartnic
Users that are interested in fa18-smartnic are comparing it to the libraries listed below
Sorting:
- P4 compatible HLS modules☆11Updated 7 years ago
- Networking Template Library for Vivado HLS☆28Updated 5 years ago
- ☆33Updated 4 years ago
- corundum work on vu13p☆19Updated last year
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆26Updated 2 years ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 7 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 10 months ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆103Updated 2 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated last week
- ☆19Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- An FPGA-based NetTLP adapter☆26Updated 5 years ago
- ☆15Updated 3 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago
- cycle accurate Network-on-Chip Simulator☆28Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 5 years ago
- ☆10Updated 2 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆37Updated 6 years ago
- ☆23Updated 3 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated last month
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆12Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated 2 years ago
- ☆33Updated 9 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago