ucb-ee290c / fa18-smartnic
SmartNIC
☆14Updated 6 years ago
Alternatives and similar repositories for fa18-smartnic:
Users that are interested in fa18-smartnic are comparing it to the libraries listed below
- Networking Template Library for Vivado HLS☆28Updated 4 years ago
- An FPGA-based NetTLP adapter☆25Updated 5 years ago
- ☆19Updated 4 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 7 years ago
- corundum work on vu13p☆18Updated last year
- P4 compatible HLS modules☆11Updated 6 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆20Updated 4 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 3 years ago
- ☆33Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆20Updated 6 years ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 6 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 7 months ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- The official NaplesPU hardware code repository☆15Updated 5 years ago
- ☆14Updated 2 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆20Updated last week
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- An Agile Chisel-Based SoC Design Framework☆26Updated 3 years ago
- ☆62Updated last month
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- ☆30Updated 9 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆22Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- ☆51Updated 8 months ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Updated 7 years ago
- An infrastructure for inline acceleration of network applications☆30Updated 3 years ago