ucb-ee290c / fa18-smartnic
SmartNIC
☆14Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for fa18-smartnic
- P4 compatible HLS modules☆10Updated 6 years ago
- Networking Template Library for Vivado HLS☆28Updated 4 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆19Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 5 years ago
- ☆14Updated 2 years ago
- ☆10Updated last year
- A parallel and distributed simulator for thousand-core chips☆22Updated 6 years ago
- ☆18Updated 3 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆12Updated 2 months ago
- ☆18Updated 5 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- ☆30Updated 8 years ago
- Verilog PCI express components☆18Updated last year
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆19Updated 4 years ago
- An FPGA-based NetTLP adapter☆21Updated 4 years ago
- An Agile Chisel-Based SoC Design Framework☆26Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 2 months ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆10Updated 6 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- corundum work on vu13p☆17Updated last year
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆19Updated 2 weeks ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- ☆32Updated 3 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆33Updated 6 years ago
- An infrastructure for inline acceleration of network applications☆30Updated 3 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 8 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆18Updated this week