ucb-ee290c / fa18-smartnicLinks
SmartNIC
☆14Updated 6 years ago
Alternatives and similar repositories for fa18-smartnic
Users that are interested in fa18-smartnic are comparing it to the libraries listed below
Sorting:
- P4 compatible HLS modules☆11Updated 7 years ago
- Networking Template Library for Vivado HLS☆29Updated 5 years ago
- ☆35Updated 4 years ago
- A parallel and distributed simulator for thousand-core chips☆26Updated 7 years ago
- corundum work on vu13p☆21Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆19Updated 6 years ago
- ☆19Updated 4 years ago
- An FPGA-based NetTLP adapter☆26Updated 5 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated last week
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 6 years ago
- ☆35Updated 9 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆40Updated 7 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆11Updated 9 years ago
- FPGA-based HyperLogLog Accelerator☆12Updated 5 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 3 weeks ago
- ☆13Updated 10 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 10 years ago
- ☆15Updated 3 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ☆13Updated 10 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆43Updated 8 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- ☆10Updated 2 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 6 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago