openrisc / or1k_marocchinoLinks
OpenRISC processor IP core based on Tomasulo algorithm
☆32Updated 3 years ago
Alternatives and similar repositories for or1k_marocchino
Users that are interested in or1k_marocchino are comparing it to the libraries listed below
Sorting:
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 10 months ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Yet Another RISC-V Implementation☆93Updated 8 months ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- Open Processor Architecture☆26Updated 9 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 3 weeks ago
- Platform Level Interrupt Controller☆40Updated last year
- ☆36Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆42Updated 5 months ago
- An implementation of RISC-V☆33Updated last week
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 7 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Announcements related to Verilator☆39Updated 5 years ago