openrisc / or1k_marocchinoLinks
OpenRISC processor IP core based on Tomasulo algorithm
☆32Updated 3 years ago
Alternatives and similar repositories for or1k_marocchino
Users that are interested in or1k_marocchino are comparing it to the libraries listed below
Sorting:
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- An implementation of RISC-V☆34Updated this week
- Parallel Array of Simple Cores. Multicore processor.☆100Updated 6 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆44Updated last month
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- Mutation Cover with Yosys (MCY)☆85Updated this week
- ☆37Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 6 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- ☆79Updated last year
- FuseSoC standard core library☆144Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- Using ModelSim Foreign Language Interface for c – VHDL Co-Simulation and for Simulator Control on Linux x86 Platform☆27Updated 4 years ago
- Platform Level Interrupt Controller☆41Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆109Updated last month
- An automatic clock gating utility☆50Updated 2 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ☆113Updated 4 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- RISC-V processor☆31Updated 3 years ago