dai-pch / FSM
A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.
☆13Updated 3 years ago
Alternatives and similar repositories for FSM:
Users that are interested in FSM are comparing it to the libraries listed below
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- ☆64Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- FFT generator using Chisel☆57Updated 3 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆14Updated 6 years ago
- Chisel implementation of AES☆23Updated 4 years ago
- ☆42Updated 3 years ago
- Craft 2 top-level repository☆13Updated 5 years ago
- ☆24Updated 5 years ago
- ☆32Updated this week
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- ☆29Updated 5 years ago
- scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.☆15Updated 2 years ago
- ☆20Updated 5 years ago
- ☆23Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Contains commonly used UVM components (agents, environments and tests).☆27Updated 6 years ago
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆16Updated 4 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated last month
- Pure digital components of a UCIe controller☆55Updated this week
- ☆20Updated 5 years ago
- ☆21Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆59Updated 5 years ago