IA-C-Lab-Fudan / Chisel-FFT-generator
FFT generator using Chisel
☆57Updated 3 years ago
Alternatives and similar repositories for Chisel-FFT-generator:
Users that are interested in Chisel-FFT-generator are comparing it to the libraries listed below
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆88Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆58Updated 6 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- AXI总线连接器☆94Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- ☆70Updated 10 years ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago
- 3×3脉动阵列乘法器☆37Updated 5 years ago
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- ☆64Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆66Updated last year
- A verilog implementation for Network-on-Chip☆71Updated 7 years ago
- Some useful documents of Synopsys☆62Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- ☆29Updated 5 years ago
- ☆23Updated 2 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆79Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆49Updated last year
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆41Updated last year
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆23Updated last year
- AXI Interconnect☆47Updated 3 years ago