plex1 / SpinalDevLinks
Docker Development Environment for SpinalHDL
☆20Updated last year
Alternatives and similar repositories for SpinalDev
Users that are interested in SpinalDev are comparing it to the libraries listed below
Sorting:
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆52Updated last week
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆30Updated 7 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Updated 8 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- Spen's Official OpenOCD Mirror☆51Updated 9 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- ☆38Updated 3 years ago
- Wishbone interconnect utilities☆44Updated 3 weeks ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆63Updated last month
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- Extensible FPGA control platform