plex1 / SpinalDev
Docker Development Environment for SpinalHDL
☆18Updated last month
Related projects: ⓘ
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆21Updated 9 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 2 months ago
- demo project to show how to use vivado tcl scripts to do everything.☆11Updated 8 years ago
- ☆25Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 3 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆59Updated last week
- A Python package for generating HDL wrappers and top modules for HDL sources☆22Updated this week
- ☆35Updated 2 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆45Updated 3 months ago
- Platform Level Interrupt Controller☆34Updated 4 months ago
- ☆24Updated 2 years ago
- Generate Zynq configurations without using the vendor GUI☆29Updated last year
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- Flip flop setup, hold & metastability explorer tool☆31Updated last year
- A padring generator for ASICs☆22Updated last year
- Python script to transform a VCD file to wavedrom format☆68Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- ☆29Updated 3 years ago
- ☆12Updated 3 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆26Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆28Updated last year
- Drive a Wishbone master bus with an SPI bus.☆10Updated 2 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆16Updated 5 years ago
- ☆21Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆25Updated 8 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆38Updated 3 months ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆32Updated 6 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆34Updated last year