Alternatives and similar repositories for SpinalDev

Users that are interested in SpinalDev are comparing it to the libraries listed below

• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆34Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆94Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆37Updated 3 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆92Updated 6 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated last month
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆51Updated 10 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆64Updated 2 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆56Updated this week
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆53Updated this week
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆70Updated last month
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆30Updated 7 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆51Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆42Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• wyvernSemi / usbModel
  USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL
  ☆32Updated last year
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• hdlguy / vivado_tcl
  demo project to show how to use vivado tcl scripts to do everything.
  ☆17Updated 10 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆18Updated 8 years ago