plex1 / SpinalDevLinks
Docker Development Environment for SpinalHDL
☆20Updated last year
Alternatives and similar repositories for SpinalDev
Users that are interested in SpinalDev are comparing it to the libraries listed below
Sorting:
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated 2 weeks ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Xilinx Unisim Library in Verilog☆84Updated 5 years ago
- USB virtual model in C++ for Verilog☆31Updated 10 months ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- UART models for cocotb☆29Updated 2 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 9 years ago
- Wishbone interconnect utilities☆41Updated 6 months ago
- demo project to show how to use vivado tcl scripts to do everything.☆17Updated 9 years ago
- Advanced Debug Interface☆15Updated 7 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Yet Another RISC-V Implementation☆96Updated 11 months ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆29Updated 6 years ago
- ☆12Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated last month
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆57Updated 2 weeks ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- Spen's Official OpenOCD Mirror☆50Updated 5 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- ☆38Updated 3 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 6 months ago