FPGA-House-AG / SpinalCorundumLinks
SpinalHDL components for Corundum Ethernet
☆13Updated 2 years ago
Alternatives and similar repositories for SpinalCorundum
Users that are interested in SpinalCorundum are comparing it to the libraries listed below
Sorting:
- ☆20Updated 2 years ago
- ☆76Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆25Updated last year
- AXI Stream UART (verilog)☆11Updated 5 years ago
- ☆24Updated 2 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆30Updated last year
- ☆27Updated 4 years ago
- Verilog Ethernet Switch (layer 2)☆46Updated last year
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 3 months ago
- Implementation of the PCIe physical layer☆49Updated last month
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆16Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Updated 7 years ago
- Open FPGA Modules☆24Updated 10 months ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 5 months ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- List of SpinalHDL projects, libraries, and learning resources.☆17Updated 5 months ago
- Chisel Things for OFDM☆32Updated 5 years ago
- NVMe Controller featuring Hardware Acceleration☆93Updated 4 years ago
- IEEE P1735 decryptor for VHDL☆36Updated 10 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- 10GbE XGMII TCP/IPv4 packet generator for Verilog☆23Updated 7 months ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago