ucb-bar / dsptools

Related projects ⓘ

Alternatives and complementary repositories for dsptools

• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆223Updated 3 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated last year
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 3 months ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆148Updated 9 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆177Updated this week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆115Updated last year
• ucb-bar / berkeley-hardfloat
  ☆291Updated 2 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆232Updated 2 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆127Updated last month
• sifive / sifive-blocks
  Common RTL blocks used in SiFive's projects
  ☆179Updated 2 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆142Updated last week
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆119Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆167Updated 2 months ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆209Updated 4 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆107Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆251Updated this week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆255Updated last week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• ucb-bar / testchipip
  ☆80Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆167Updated 4 months ago
• sifive / block-inclusivecache-sifive
  ☆75Updated 2 years ago
• sifive / fpga-shells
  ☆131Updated 2 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆438Updated 3 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆288Updated 5 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆230Updated 2 weeks ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆153Updated 4 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆217Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆225Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆106Updated 2 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆176Updated 2 weeks ago