Alternatives and similar repositories for dsptools

Users that are interested in dsptools are comparing it to the libraries listed below

• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated last year
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆265Updated 3 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• ucb-bar / berkeley-hardfloat
  ☆362Updated 3 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆223Updated 2 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆159Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆206Updated last year
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆161Updated last year
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆151Updated last year
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆308Updated 2 months ago
• ucb-bar / testchipip
  ☆87Updated last week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆187Updated 2 weeks ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆219Updated 5 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated 3 months ago
• SpinalHDL / NaxRiscv
  ☆301Updated last month
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆88Updated 4 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆401Updated 6 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆257Updated 3 weeks ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆144Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆352Updated 2 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 7 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆310Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆196Updated 3 years ago