Alternatives and similar repositories for dsptools:

Users that are interested in dsptools are comparing it to the libraries listed below

• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 8 months ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆151Updated last year
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated 8 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆251Updated 2 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆194Updated last month
• ucb-bar / berkeley-hardfloat
  ☆319Updated 7 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆148Updated 5 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆209Updated 5 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆190Updated 9 months ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆136Updated 7 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆172Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 5 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆321Updated 10 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆250Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆175Updated 4 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆225Updated 5 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆480Updated 2 months ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆122Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆194Updated 3 weeks ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆277Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 9 months ago
• ucb-bar / testchipip
  ☆83Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆275Updated last year
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago