Alternatives and similar repositories for dsptools:

Users that are interested in dsptools are comparing it to the libraries listed below

• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 7 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 7 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆191Updated 3 weeks ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆118Updated last year
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆151Updated last year
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆249Updated 2 years ago
• ucb-bar / berkeley-hardfloat
  ☆312Updated 6 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆186Updated 8 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆174Updated 4 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆147Updated 4 months ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆133Updated 6 months ago
• ucb-bar / testchipip
  ☆82Updated last week
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆122Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆210Updated 5 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆469Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆269Updated 2 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆172Updated 8 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆248Updated 3 weeks ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆194Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 4 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆274Updated last year
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆83Updated 2 weeks ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆309Updated 3 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆318Updated 9 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆270Updated last week