Alternatives and similar repositories for cva6-wrapper:

Users that are interested in cva6-wrapper are comparing it to the libraries listed below

• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 9 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated 2 weeks ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆17Updated 4 months ago
• firesim / icenet
  Network components (NIC, Switch) for FireBox
  ☆16Updated 5 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆19Updated last week
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated 11 months ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆18Updated this week
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• Chlorophytus / broccoli
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated this week
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆18Updated 2 months ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 9 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆38Updated 2 years ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 4 years ago
• pulp-platform / hci
  Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
  ☆13Updated last week
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 11 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated last week
• ucb-bar / fixedpoint
  Chisel Fixed-Point Arithmetic Library
  ☆13Updated 2 months ago
• carlosedp / riscvassembler
  A RISC-V assembler library for Scala/Chisel HDL projects
  ☆13Updated last week
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated last year
• ucb-bar / chisel-awl
  ☆13Updated 4 years ago
• ducky64 / chisualizer
  Block-diagram style digital logic visualizer
  ☆23Updated 9 years ago
• joey1115 / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆12Updated 5 years ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆84Updated this week
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago