Alternatives and similar repositories for cva6-wrapper:

Users that are interested in cva6-wrapper are comparing it to the libraries listed below

• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆30Updated this week
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 8 months ago
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆19Updated last year
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆17Updated 3 months ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated 10 months ago
• firesim / icenet
  Network components (NIC, Switch) for FireBox
  ☆16Updated 4 months ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆17Updated last month
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆18Updated last week
• Chlorophytus / broccoli
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated last week
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆38Updated 2 years ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 4 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆38Updated 3 months ago
• IBM / perfect-chisel
  Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
  ☆30Updated 2 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆37Updated this week
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆84Updated this week
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated last week
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆31Updated last week
• stanford-ppl / pir
  ☆15Updated last year
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• pulp-platform / hci
  Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
  ☆12Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 4 months ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• freechipsproject / www.chisel-lang.org
  The home of the Chisel3 website
  ☆20Updated 9 months ago
• pulp-platform / redmule
  ☆47Updated this week