IBM / chiffreLinks
A fault-injection framework using Chisel and FIRRTL
☆36Updated 2 months ago
Alternatives and similar repositories for chiffre
Users that are interested in chiffre are comparing it to the libraries listed below
Sorting:
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- Useful utilities for BAR projects☆32Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Updated 2 months ago
- A Rocket-based RISC-V superscalar in-order core☆33Updated 2 months ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 3 weeks ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- ☆14Updated 4 years ago
- Chisel Things for OFDM☆32Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- A configurable SRAM generator☆53Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- sram/rram/mram.. compiler☆35Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆29Updated 5 months ago
- The home of the Chisel3 website☆20Updated last year
- The specification for the FIRRTL language☆58Updated last week
- ☆15Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- A prototype GUI for chisel-development☆52Updated 5 years ago
- ☆81Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 2 months ago