IBM / chiffre
A fault-injection framework using Chisel and FIRRTL
☆34Updated 2 years ago
Alternatives and similar repositories for chiffre:
Users that are interested in chiffre are comparing it to the libraries listed below
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Useful utilities for BAR projects☆30Updated last year
- ☆15Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- A Rocket-based RISC-V superscalar in-order core☆29Updated last week
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- ☆54Updated 2 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- A configurable SRAM generator☆42Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- The RTL source for AnyCore RISC-V☆30Updated 2 years ago
- The specification for the FIRRTL language☆51Updated this week
- ☆77Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 5 years ago
- Simple UVM environment for experimenting with Verilator.☆16Updated last month
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 2 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- ☆32Updated last week
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Updated 4 years ago