IBM / chiffreLinks
A fault-injection framework using Chisel and FIRRTL
☆36Updated 3 months ago
Alternatives and similar repositories for chiffre
Users that are interested in chiffre are comparing it to the libraries listed below
Sorting:
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- A Rocket-based RISC-V superscalar in-order core☆36Updated 3 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- Useful utilities for BAR projects☆32Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- ☆12Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- Intel Compiler for SystemC☆27Updated 2 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- A configurable SRAM generator☆56Updated 4 months ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- A vector processor implemented in Chisel☆21Updated 11 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- ☆82Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Updated 3 months ago
- ☆59Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- A prototype GUI for chisel-development☆51Updated 5 years ago