IBM / chiffre
A fault-injection framework using Chisel and FIRRTL
☆34Updated 2 years ago
Alternatives and similar repositories for chiffre:
Users that are interested in chiffre are comparing it to the libraries listed below
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- Useful utilities for BAR projects☆31Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆30Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆31Updated 2 weeks ago
- ☆55Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 5 years ago
- The specification for the FIRRTL language☆51Updated last week
- Simple UVM environment for experimenting with Verilator.☆18Updated 2 months ago
- ☆15Updated 4 years ago
- A configurable SRAM generator☆47Updated 2 months ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 6 years ago
- The home of the Chisel3 website☆20Updated 9 months ago
- sram/rram/mram.. compiler☆31Updated last year
- Tests for example Rocket Custom Coprocessors☆72Updated 5 years ago
- Chisel Cheatsheet☆33Updated last year
- The RTL source for AnyCore RISC-V☆31Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago