Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
☆24Feb 1, 2020Updated 6 years ago
Alternatives and similar repositories for esp-chisel-accelerators
Users that are interested in esp-chisel-accelerators are comparing it to the libraries listed below
Sorting:
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- ☆12May 20, 2021Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 5 months ago
- Useful utilities for BAR projects☆32Jan 3, 2024Updated 2 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 5 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 5 months ago
- Chisel Things for OFDM☆32Jul 1, 2020Updated 5 years ago
- ☆11Feb 16, 2019Updated 7 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- ☆14Aug 31, 2025Updated 6 months ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 6 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- For contributions of Chisel IP to the chisel community.☆71Nov 7, 2024Updated last year
- hardware (ASIC) DEFLATE designed for low-latency page-granularity memory compression and implemented in Chisel☆16Nov 15, 2024Updated last year
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- ☆110Oct 19, 2018Updated 7 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Sep 17, 2025Updated 5 months ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Jul 17, 2016Updated 9 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- ☆19Jul 12, 2024Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 3 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 7 years ago
- Floating point modules for CHISEL☆32Nov 2, 2014Updated 11 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Dec 22, 2025Updated 2 months ago
- A time-predictable processor for mixed-criticality systems☆60Nov 7, 2024Updated last year
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 8 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated this week
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆129Updated this week
- eyeriss-chisel3☆40May 2, 2022Updated 3 years ago
- Chisel components for FPGA projects☆128Sep 19, 2023Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year