IBM / esp-chisel-acceleratorsLinks
Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
☆24Updated 5 years ago
Alternatives and similar repositories for esp-chisel-accelerators
Users that are interested in esp-chisel-accelerators are comparing it to the libraries listed below
Sorting:
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 6 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- A vector processor implemented in Chisel☆21Updated 10 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Updated 5 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated this week
- CNN accelerator☆27Updated 8 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆25Updated this week
- Advanced Debug Interface☆15Updated 5 months ago
- ☆14Updated 3 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 11 months ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- ☆20Updated 5 years ago
- sram/rram/mram.. compiler☆35Updated last year
- ☆12Updated 4 years ago
- ☆30Updated 2 months ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Intel Compiler for SystemC☆23Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Chisel Things for OFDM☆32Updated 4 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago