IBM / esp-chisel-accelerators
Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
☆24Updated 5 years ago
Alternatives and similar repositories for esp-chisel-accelerators:
Users that are interested in esp-chisel-accelerators are comparing it to the libraries listed below
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- ☆20Updated 5 years ago
- sram/rram/mram.. compiler☆33Updated last year
- ☆14Updated last month
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- A vector processor implemented in Chisel☆21Updated 10 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 9 months ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuites☆12Updated 6 years ago
- ☆27Updated 3 weeks ago
- CNN accelerator☆28Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Advanced Debug Interface☆14Updated 3 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Chisel Things for OFDM☆31Updated 4 years ago
- ☆14Updated 4 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago