ucb-bar / midas
FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
☆101Updated 5 years ago
Alternatives and similar repositories for midas:
Users that are interested in midas are comparing it to the libraries listed below
- Chisel/Firrtl execution engine☆153Updated 8 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated 3 weeks ago
- Provides various testers for chisel users☆100Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆156Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- ☆102Updated 2 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆48Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated 9 months ago
- A Library of Chisel3 Tools for Digital Signal Processing☆236Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- Main page☆126Updated 5 years ago
- Bluespec BSV HLHDL tutorial☆103Updated 9 years ago
- Lipsi: Probably the Smallest Processor in the World☆84Updated last year
- Next generation CGRA generator☆111Updated this week
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆80Updated 5 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆87Updated 2 years ago
- (System)Verilog to Chisel translator☆113Updated 2 years ago
- ☆84Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆153Updated last year
- Chisel components for FPGA projects☆122Updated last year
- Connectal is a framework for software-driven hardware development.☆168Updated last year
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆103Updated 5 months ago
- OpenSoC Fabric - A Network-On-Chip Generator☆164Updated 4 years ago
- high-performance RTL simulator☆157Updated 10 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆120Updated 10 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆252Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆226Updated 5 months ago