FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
☆103Nov 22, 2019Updated 6 years ago
Alternatives and similar repositories for midas
Users that are interested in midas are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A scala based simulator for circuits described by a LoFirrtl file☆50Jan 12, 2023Updated 3 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- MIDAS Public Release☆11Nov 27, 2018Updated 7 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆249Apr 29, 2024Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Fluid Pipelines☆11May 4, 2018Updated 8 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆321Mar 6, 2026Updated 3 months ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆31Sep 17, 2025Updated 8 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Jan 6, 2022Updated 4 years ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- Governance-related CHIPS Alliance documents, guides etc.☆10Feb 20, 2023Updated 3 years ago
- Flexible Intermediate Representation for RTL☆750Aug 20, 2024Updated last year
- ☆13Feb 13, 2021Updated 5 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,019Updated this week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆154Jan 8, 2026Updated 5 months ago
- ☆111Oct 19, 2018Updated 7 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 9 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Block-diagram style digital logic visualizer☆23Sep 16, 2015Updated 10 years ago
- educational microarchitectures for risc-v isa☆748Sep 1, 2025Updated 9 months ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆38Sep 17, 2025Updated 8 months ago
- Useful utilities for BAR projects☆32Jan 3, 2024Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆301May 28, 2026Updated 2 weeks ago
- Lipsi: Probably the Smallest Processor in the World☆89Apr 15, 2024Updated 2 years ago
- high-performance RTL simulator☆193Jun 19, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Chisel components for FPGA projects☆129Sep 19, 2023Updated 2 years ago
- The root repo for lowRISC project and FPGA demos.☆600Aug 3, 2023Updated 2 years ago
- Chisel Things for OFDM☆33Jul 1, 2020Updated 5 years ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- (System)Verilog to Chisel translator☆121May 20, 2022Updated 4 years ago
- ☆20Mar 1, 2021Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago