ucb-bar / midasLinks
FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
☆101Updated 6 years ago
Alternatives and similar repositories for midas
Users that are interested in midas are comparing it to the libraries listed below
Sorting:
- Chisel/Firrtl execution engine☆155Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated 3 weeks ago
- Provides various testers for chisel users☆100Updated 3 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆183Updated 8 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- ☆104Updated 3 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 3 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 3 months ago
- ☆87Updated this week
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- Main page☆129Updated 5 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Chisel components for FPGA projects☆128Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated 2 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆244Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆173Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- Open-source FPGA research and prototyping framework.☆211Updated last year
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆120Updated 8 months ago
- Useful utilities for BAR projects☆32Updated 2 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 8 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆175Updated 5 years ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- ☆88Updated 3 years ago