ucb-bar / midasLinks
FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
☆101Updated 5 years ago
Alternatives and similar repositories for midas
Users that are interested in midas are comparing it to the libraries listed below
Sorting:
- Chisel/Firrtl execution engine☆153Updated 9 months ago
- Provides various testers for chisel users☆100Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated 3 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated this week
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- Chisel components for FPGA projects☆124Updated last year
- ☆87Updated 2 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆48Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆156Updated 4 years ago
- ☆103Updated 2 years ago
- Bluespec BSV HLHDL tutorial☆104Updated 9 years ago
- ☆84Updated 3 weeks ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- (System)Verilog to Chisel translator☆114Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Next generation CGRA generator☆111Updated this week
- A Library of Chisel3 Tools for Digital Signal Processing☆236Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆82Updated this week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 8 months ago
- Main page☆126Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- A dynamic verification library for Chisel.☆151Updated 6 months ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆122Updated 11 months ago
- RISC-V Torture Test☆195Updated 10 months ago