nhynes / chisel3-axi
Chisel3 AXI4-{Lite, Full, Stream} Definitions
☆15Updated 6 years ago
Alternatives and similar repositories for chisel3-axi
Users that are interested in chisel3-axi are comparing it to the libraries listed below
Sorting:
- ☆33Updated last month
- Chisel Cheatsheet☆33Updated 2 years ago
- ☆17Updated 3 years ago
- A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.☆13Updated 3 years ago
- ☆19Updated 3 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- An almost empty chisel project as a starting point for hardware design☆30Updated 3 months ago
- A prototype GUI for chisel-development☆52Updated 4 years ago
- Run Rocket Chip on VCU128☆30Updated 5 months ago
- ☆39Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- ☆20Updated 2 months ago
- ☆20Updated 5 years ago
- The 'missing header' for Chisel☆20Updated last month
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated last month
- ☆27Updated last month
- ☆21Updated 4 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆29Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆53Updated 3 years ago
- Advanced Architecture Labs with CVA6☆59Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated 2 weeks ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆19Updated 4 years ago
- ☆40Updated 3 months ago
- Hardware design with Chisel☆32Updated 2 years ago
- ☆18Updated 2 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Updated 3 years ago