Alternatives and similar repositories for goParseBSV

Users that are interested in goParseBSV are comparing it to the libraries listed below

• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 9 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆35Updated 4 months ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated last week
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆59Updated 8 months ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆29Updated 8 months ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• drom / reqack
  🔁 elastic circuit toolchain
  ☆31Updated 7 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• carlosedp / chisel-playground
  Chisel HDL example applications
  ☆30Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 months ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 5 years ago
• bluespec / AWSteria_Infra
  "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)
  ☆19Updated 9 months ago
• CTSRD-CHERI / BlueStuff
  A Bluespec SystemVerilog library of miscellaneous components
  ☆16Updated 3 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated 2 weeks ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆48Updated 2 years ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆12Updated 4 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year