rsnikhil / goParseBSV
A standalone parser for BSV (Bluespec SystemVerilog) written in Go
☆13Updated 8 years ago
Alternatives and similar repositories for goParseBSV
Users that are interested in goParseBSV are comparing it to the libraries listed below
Sorting:
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆16Updated last month
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆18Updated 7 months ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Useful utilities for BAR projects☆31Updated last year
- RISC-V BSV Specification☆20Updated 5 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- SCARV: a side-channel hardened RISC-V platform☆26Updated 2 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated 2 months ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last week
- The specification for the FIRRTL language☆54Updated last week
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆29Updated 4 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- 🔁 elastic circuit toolchain☆30Updated 5 months ago
- Chisel HDL example applications☆30Updated 2 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Updated 4 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆12Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 3 weeks ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆55Updated 4 years ago
- Firrtl Syntax highlighting, Code folding and Navigate to corresponding Chisel code☆9Updated 3 years ago