m-labs / VexRiscv-verilog
Using VexRiscv without installing Scala
☆37Updated 3 years ago
Alternatives and similar repositories for VexRiscv-verilog:
Users that are interested in VexRiscv-verilog are comparing it to the libraries listed below
- Wishbone interconnect utilities☆38Updated last week
- SoftCPU/SoC engine-V☆54Updated last year
- Small footprint and configurable Inter-Chip communication cores☆55Updated last month
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- PicoRV☆44Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- A padring generator for ASICs☆25Updated last year
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- CMod-S6 SoC☆37Updated 7 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆29Updated 4 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Spen's Official OpenOCD Mirror☆48Updated 11 months ago
- USB Full Speed PHY☆39Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- ☆36Updated 2 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆84Updated 6 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆88Updated 4 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆43Updated last week
- ☆59Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆13Updated last month
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Wishbone controlled I2C controllers☆45Updated 3 months ago
- VexRiscv-SMP integration test with LiteX.☆25Updated 4 years ago