Alternatives and similar repositories for VexRiscv-verilog

Users that are interested in VexRiscv-verilog are comparing it to the libraries listed below

• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 5 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 4 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated last month
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 4 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆91Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 10 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated 2 months ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 3 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 4 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆91Updated 6 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆63Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 4 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆30Updated 4 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated this week
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆43Updated 4 years ago
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆14Updated 2 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆45Updated 5 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆90Updated 6 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆98Updated last week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 2 weeks ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• bobbl / rudolv
  RISC-V processor
  ☆31Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago