m-labs / VexRiscv-verilogLinks
Using VexRiscv without installing Scala
☆38Updated 3 years ago
Alternatives and similar repositories for VexRiscv-verilog
Users that are interested in VexRiscv-verilog are comparing it to the libraries listed below
Sorting:
- Wishbone interconnect utilities☆41Updated 3 months ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- PicoRV☆44Updated 5 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated this week
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- Spen's Official OpenOCD Mirror☆50Updated 2 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 5 months ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- CMod-S6 SoC☆42Updated 7 years ago
- ☆33Updated 2 years ago
- ☆36Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Docker Development Environment for SpinalHDL☆20Updated 9 months ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆28Updated 6 years ago
- Demo SoC for SiliconCompiler.☆59Updated last week
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Updated last week
- USB Full Speed PHY☆44Updated 5 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆45Updated last year
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- ☆22Updated 3 weeks ago