zhemao / riscv-dma
A DMA Controller for RISCV CPUs
☆14Updated 9 years ago
Alternatives and similar repositories for riscv-dma:
Users that are interested in riscv-dma are comparing it to the libraries listed below
- ☆13Updated 4 years ago
- Advanced Debug Interface☆14Updated 2 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- A coverage library for Chisel designs☆11Updated 5 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- The RTL source for AnyCore RISC-V☆31Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 5 years ago
- ☆10Updated 3 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 3 years ago
- ☆24Updated last month
- Useful utilities for BAR projects☆31Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆31Updated last month
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last week
- ☆21Updated 7 years ago
- Universal Advanced JTAG Debug Interface☆17Updated 10 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 5 years ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 8 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆35Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Chisel NVMe controller☆16Updated 2 years ago