The-OpenROAD-Project / OpenROAD-CloudLinks
The source code that empowers OpenROAD Cloud
☆12Updated 5 years ago
Alternatives and similar repositories for OpenROAD-Cloud
Users that are interested in OpenROAD-Cloud are comparing it to the libraries listed below
Sorting:
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 weeks ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15Updated 7 years ago
- Open Source Detailed Placement engine☆12Updated 5 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆15Updated 3 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 2 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- ☆18Updated 5 years ago
- Example of how to use UVM with Verilator☆31Updated last month
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆32Updated 2 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- The home of the Chisel3 website☆21Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- Source-Opened RISCV for Crypto☆18Updated 3 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 5 years ago
- ☆38Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24Updated 5 years ago
- LibreSilicon's Standard Cell Library Generator☆22Updated 2 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- Extended and external tests for Verilator testing☆17Updated last week
- ☆19Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- RISC-V processor☆32Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last week