Alternatives and similar repositories for OpenROAD-Cloud

Users that are interested in OpenROAD-Cloud are comparing it to the libraries listed below

• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆12Updated 5 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 5 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆18Updated 10 months ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 7 years ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆46Updated 3 months ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated last month
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 9 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆49Updated 2 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated 2 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆23Updated 2 months ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 4 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 4 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• idea-fasoc / fasoc
  ☆55Updated last year
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆20Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated last month
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆23Updated 5 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 9 months ago
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆16Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago