The-OpenROAD-Project / OpenROAD-CloudLinks
The source code that empowers OpenROAD Cloud
☆12Updated 5 years ago
Alternatives and similar repositories for OpenROAD-Cloud
Users that are interested in OpenROAD-Cloud are comparing it to the libraries listed below
Sorting:
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- Open Source Detailed Placement engine☆12Updated 5 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Updated last month
- Extended and external tests for Verilator testing☆17Updated 2 weeks ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Updated 3 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 5 years ago
- ☆19Updated last year
- Source-Opened RISCV for Crypto☆18Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆14Updated 6 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Updated last month
- IRSIM switch-level simulator for digital circuits☆35Updated 2 months ago
- ☆18Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆51Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆56Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15Updated 7 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 5 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24Updated 5 years ago
- ☆17Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago