Alternatives and similar repositories for chisel-gui:

Users that are interested in chisel-gui are comparing it to the libraries listed below

• sequencer / arithmetic
  ☆32Updated 3 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆69Updated 4 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆119Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆57Updated 2 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆101Updated 2 years ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆73Updated 9 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated last month
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• chipsalliance / tilelink
  ☆27Updated last month
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆50Updated this week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated last year
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 4 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆54Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• ucb-bar / sha3
  ☆77Updated 10 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆143Updated 2 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 5 months ago
• yamak / axi-nodes
  ☆19Updated 2 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆30Updated 2 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆30Updated 2 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆50Updated 4 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆109Updated 2 years ago
• rhit-neuro / deca
  ☆21Updated 4 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆58Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆49Updated 3 years ago
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆14Updated 10 months ago