cnrv / CNRV-FPUView external linksLinks
Basic floating-point components for RISC-V processors
☆67Dec 4, 2019Updated 6 years ago
Alternatives and similar repositories for CNRV-FPU
Users that are interested in CNRV-FPU are comparing it to the libraries listed below
Sorting:
- Basic floating-point components for RISC-V processors☆11Aug 13, 2017Updated 8 years ago
- double_fpu_verilog☆20Jul 17, 2014Updated 11 years ago
- ☆14Feb 24, 2025Updated 11 months ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- For CPU experiment☆14Feb 23, 2021Updated 4 years ago
- ☆58Feb 18, 2019Updated 6 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- Chisel Things for OFDM☆32Jul 1, 2020Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆25Sep 9, 2025Updated 5 months ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 5 years ago
- RISC-V GPGPU☆36Mar 6, 2020Updated 5 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆569Oct 21, 2025Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Jan 2, 2026Updated last month
- ☆42Mar 31, 2025Updated 10 months ago
- IEEE 754 floating point unit in Verilog☆149May 20, 2016Updated 9 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 8 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Aug 8, 2017Updated 8 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- ☆367Sep 12, 2025Updated 5 months ago
- CPUs☆16Dec 21, 2020Updated 5 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- 《关于浮点运算:作为程序员都应该了解什么?》☆27Apr 17, 2018Updated 7 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆62Jun 27, 2025Updated 7 months ago
- synthesiseable ieee 754 floating point library in verilog☆717Mar 13, 2023Updated 2 years ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- liberty介绍--LIBERATE工具使用☆18Jul 22, 2019Updated 6 years ago
- SystemC/TLM-2.0 Co-simulation framework☆268May 21, 2025Updated 8 months ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆372Jul 12, 2017Updated 8 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Jan 25, 2024Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆92Jul 3, 2019Updated 6 years ago
- SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...☆30Dec 9, 2021Updated 4 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Dec 22, 2025Updated last month