cnrv / CNRV-FPULinks
Basic floating-point components for RISC-V processors
☆66Updated 5 years ago
Alternatives and similar repositories for CNRV-FPU
Users that are interested in CNRV-FPU are comparing it to the libraries listed below
Sorting:
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- ☆67Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- ☆96Updated 2 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆142Updated last week
- An Open-Source Design and Verification Environment for RISC-V☆84Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- General Purpose AXI Direct Memory Access☆60Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- RISC-V Verification Interface☆108Updated this week
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated last month
- Vector processor for RISC-V vector ISA☆129Updated 5 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆64Updated 4 years ago
- ☆56Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 9 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- ☆65Updated 3 years ago