cnrv / CNRV-FPULinks
Basic floating-point components for RISC-V processors
☆66Updated 5 years ago
Alternatives and similar repositories for CNRV-FPU
Users that are interested in CNRV-FPU are comparing it to the libraries listed below
Sorting:
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆43Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- ☆64Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago
- ☆52Updated 6 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆174Updated last month
- ☆66Updated 3 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆62Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- ☆90Updated last week
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- Network on Chip Implementation written in SytemVerilog☆188Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 11 months ago
- Pure digital components of a UCIe controller☆67Updated last month
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆169Updated this week
- An Open-Source Design and Verification Environment for RISC-V☆83Updated 4 years ago
- Chisel components for FPGA projects☆126Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆57Updated last year
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago