pretis / flexpret
A time-predictable processor for mixed-criticality systems
☆58Updated 4 months ago
Alternatives and similar repositories for flexpret:
Users that are interested in flexpret are comparing it to the libraries listed below
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆139Updated 2 weeks ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆47Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆83Updated 10 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆80Updated this week
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Open Processor Architecture☆26Updated 8 years ago
- ☆23Updated 4 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆35Updated 5 months ago
- OmniXtend cache coherence protocol☆78Updated 4 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆33Updated this week
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆154Updated 4 years ago
- ☆45Updated 2 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆64Updated 2 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆99Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- ☆55Updated 2 years ago
- An implementation of RISC-V☆25Updated this week