pretis / flexpretLinks
A time-predictable processor for mixed-criticality systems
☆60Updated last year
Alternatives and similar repositories for flexpret
Users that are interested in flexpret are comparing it to the libraries listed below
Sorting:
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last month
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 8 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆37Updated 2 months ago
- Mutation Cover with Yosys (MCY)☆89Updated last month
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- BSC Development Workstation (BDW)☆32Updated 2 months ago
- Main page☆129Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆169Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆34Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- An implementation of RISC-V☆46Updated last month
- ☆51Updated this week
- Useful utilities for BAR projects☆32Updated 2 years ago
- FPGA tool performance profiling☆104Updated last year
- educational microarchitectures for risc-v isa☆67Updated 6 years ago