SpinalHDL / SpinalDocLinks
SpinalHDL documentation assets (pictures, slides, ...)
☆33Updated 9 months ago
Alternatives and similar repositories for SpinalDoc
Users that are interested in SpinalDoc are comparing it to the libraries listed below
Sorting:
- Labs to learn SpinalHDL☆149Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆88Updated 2 years ago
- UART 16550 core☆37Updated 11 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- A basic SpinalHDL project☆88Updated last month
- Verilog wishbone components☆118Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆110Updated 4 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Platform Level Interrupt Controller☆42Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- Wishbone interconnect utilities☆41Updated 7 months ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- Yet Another RISC-V Implementation☆97Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- WISHBONE SD Card Controller IP Core☆128Updated 3 years ago
- UART models for cocotb☆30Updated 2 weeks ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- Re-coded Xilinx primitives for Verilator use☆50Updated 3 months ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆95Updated this week
- Mathematical Functions in Verilog☆95Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- SpinalHDL Hardware Math Library☆90Updated last year