SpinalHDL / SpinalDocLinks
SpinalHDL documentation assets (pictures, slides, ...)
☆31Updated last year
Alternatives and similar repositories for SpinalDoc
Users that are interested in SpinalDoc are comparing it to the libraries listed below
Sorting:
- A set of Wishbone Controlled SPI Flash Controllers☆95Updated 3 years ago
- Labs to learn SpinalHDL☆151Updated last year
- WISHBONE SD Card Controller IP Core☆130Updated 3 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- UART 16550 core☆38Updated 11 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- A basic SpinalHDL project☆88Updated 4 months ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- Verilog wishbone components☆123Updated 2 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆70Updated 7 years ago
- Platform Level Interrupt Controller☆43Updated last year
- Yet Another RISC-V Implementation☆99Updated last year
- UART models for cocotb☆32Updated 4 months ago
- USB 1.1 Host and Function IP core☆24Updated 11 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Updated 2 years ago
- Wishbone interconnect utilities☆44Updated 3 weeks ago
- I2C controller core☆47Updated 3 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 10 months ago
- Small (Q)SPI flash memory programmer in Verilog☆68Updated 3 years ago
- JTAG Test Access Port (TAP)☆36Updated 11 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆85Updated last year
- AXI4 and AXI4-Lite interface definitions☆99Updated 5 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆81Updated 3 years ago
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago