Alternatives and similar repositories for SpinalDoc

Users that are interested in SpinalDoc are comparing it to the libraries listed below

• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆83Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆149Updated last year
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆125Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 5 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆79Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 9 months ago
• freecores / uart16550
  UART 16550 core
  ☆37Updated 11 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 4 years ago
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆87Updated 3 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆64Updated 5 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆93Updated 4 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆63Updated 2 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆137Updated 3 weeks ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆50Updated 3 weeks ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆35Updated 10 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆42Updated 5 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆55Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 5 months ago
• ldoolitt / vhd2vl
  ☆134Updated 7 months ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆23Updated 11 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆151Updated 4 months ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆35Updated 3 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆57Updated 2 years ago