SpinalHDL / SpinalDoc
SpinalHDL documentation assets (pictures, slides, ...)
☆32Updated 3 months ago
Alternatives and similar repositories for SpinalDoc:
Users that are interested in SpinalDoc are comparing it to the libraries listed below
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- A basic SpinalHDL project☆83Updated last week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- Labs to learn SpinalHDL☆148Updated 8 months ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- ☆81Updated 2 weeks ago
- Platform Level Interrupt Controller☆38Updated 10 months ago
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- UART 16550 core☆33Updated 10 years ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- Mathematical Functions in Verilog☆91Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆132Updated 9 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆134Updated 2 weeks ago
- Yet Another RISC-V Implementation☆91Updated 6 months ago
- JTAG Test Access Port (TAP)☆33Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆31Updated 2 months ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Verilator open-source SystemVerilog simulator and lint system☆35Updated this week
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- Basic RISC-V Test SoC☆119Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆24Updated 5 years ago
- Control and Status Register map generator for HDL projects☆114Updated last month