Alternatives and similar repositories for perfect-chisel

Users that are interested in perfect-chisel are comparing it to the libraries listed below

• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆13Updated 6 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Updated 5 years ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆31Updated 4 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• chipsalliance / espresso
  ☆41Updated 5 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 6 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• sequencer / arithmetic
  ☆33Updated 8 months ago
• ucb-bar / sha3
  ☆81Updated last year
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆87Updated last month
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• freechipsproject / www.chisel-lang.org
  The home of the Chisel3 website
  ☆21Updated last year
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 5 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated last month
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆26Updated 2 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆66Updated 3 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 10 years ago
• TsaiAnson / verif
  ☆12Updated 4 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆33Updated 3 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆127Updated 2 years ago
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆41Updated last year