IBM / perfect-chiselLinks
Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
☆30Updated 3 months ago
Alternatives and similar repositories for perfect-chisel
Users that are interested in perfect-chisel are comparing it to the libraries listed below
Sorting:
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- A prototype GUI for chisel-development☆51Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Useful utilities for BAR projects☆32Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- ☆12Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- ☆82Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 2 months ago
- Intel Compiler for SystemC☆26Updated 2 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- chipyard in mill :P☆77Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- The home of the Chisel3 website☆21Updated last year
- ☆20Updated 5 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆88Updated 2 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- ☆87Updated last week
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- A SystemVerilog source file pickler.☆60Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year