CTSRD-CHERI / axeLinks
Consistency checker for memory subsystem traces
☆22Updated 8 years ago
Alternatives and similar repositories for axe
Users that are interested in axe are comparing it to the libraries listed below
Sorting:
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆47Updated 2 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated 2 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- A scala based simulator for circuits described by a LoFirrtl file☆48Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- RISC-V BSV Specification☆20Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated last month
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆69Updated last year
- The specification for the FIRRTL language☆58Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆144Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆36Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆85Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 9 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Home of the Advanced Interface Bus (AIB) specification.☆53Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 2 months ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago