Consistency checker for memory subsystem traces
☆23Oct 10, 2016Updated 9 years ago
Alternatives and similar repositories for axe
Users that are interested in axe are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V BSV Specification☆23Jan 18, 2020Updated 6 years ago
- A tool to run litmus tests on bare-metal hardware☆13Mar 13, 2017Updated 9 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- ☆12May 20, 2021Updated 4 years ago
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Memory consistency model checking and test generation library.☆15Oct 14, 2016Updated 9 years ago
- Development area for another repo: Learn_Bluespec_and_RISCV_Design☆13Nov 10, 2025Updated 4 months ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 9 months ago
- Tools based upon slang for language server purpose☆22Mar 17, 2026Updated last week
- Arm SystemReady : BSA Architecture Compliance Suite☆29Aug 25, 2025Updated 7 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆33Apr 13, 2021Updated 4 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Oct 4, 2018Updated 7 years ago
- Chisel Things for OFDM☆32Jul 1, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- Useful utilities for BAR projects☆32Jan 3, 2024Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- An open-source custom cache generator.☆35Mar 14, 2024Updated 2 years ago
- Modular, flexible, cross-platform workload profiling and characterization☆13Mar 1, 2021Updated 5 years ago
- Binomial model☆12Aug 28, 2019Updated 6 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- RP2040 firmware for controlling GPIO over USB CDC with AT commands☆13Dec 22, 2024Updated last year
- CPU micro benchmarks☆79Feb 11, 2026Updated last month
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures☆11Apr 23, 2019Updated 6 years ago
- High quality and composable RTL libraries in SystemVerilog☆32Updated this week
- Hardware-assisted Dynamic Information Flow Tracking for Runtime Protection on RISC-V☆11Oct 16, 2023Updated 2 years ago
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- This is a Project to Integrate and Automate the functions of three tools named gem5, McPAT and HotSpot.☆10Jul 1, 2019Updated 6 years ago
- Microbenchmarking experiments on Zen 2 machines☆21Jun 25, 2022Updated 3 years ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆24Jan 17, 2025Updated last year
- Framework for writing tests for RISC-V CPU/SOC validation.☆11Jan 19, 2026Updated 2 months ago
- Clairvoyance LLVM Tools. Instruction scheduling targeting long latency loads.☆14Mar 14, 2019Updated 7 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- Alloy models for automatic synthesis of memory model litmus test suites (from ASPLOS 2017)☆16Jan 26, 2024Updated 2 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆15Mar 2, 2022Updated 4 years ago
- The BERI and CHERI processor and hardware platform☆50Mar 27, 2017Updated 9 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- Script generated finite field arithmetic for elliptic curve cryptography☆24Mar 4, 2026Updated 3 weeks ago