CTSRD-CHERI / axeLinks
Consistency checker for memory subsystem traces
☆23Updated 9 years ago
Alternatives and similar repositories for axe
Users that are interested in axe are comparing it to the libraries listed below
Sorting:
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- ☆51Updated last week
- Documentation for the BOOM processor☆47Updated 8 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆42Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 3 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last week
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- OmniXtend cache coherence protocol☆82Updated 7 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆169Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Chisel RISC-V Vector 1.0 Implementation☆126Updated 3 months ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- ☆87Updated last week
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆108Updated 3 months ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- The specification for the FIRRTL language☆62Updated last week
- RISC-V BSV Specification☆23Updated 5 years ago