CTSRD-CHERI / axe

Related projects: ⓘ

• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• ducky64 / chisualizer
  Block-diagram style digital logic visualizer
  ☆23Updated 9 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆17Updated 4 years ago
• riscv / riscv-test-env
  ☆40Updated 3 months ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆33Updated last year
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated 8 months ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• esperantotech / boom-template
  A template for building new projects/platforms using the BOOM core.
  ☆24Updated 5 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 7 years ago
• lowRISC / rocket
  ☆28Updated 6 years ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 11 months ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆56Updated 5 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 2 months ago
• chipsalliance / fpga-interchange-schema
  ☆51Updated 2 years ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆33Updated 2 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• IBM / perfect-chisel
  Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
  ☆29Updated last year
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆26Updated 4 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆33Updated 5 months ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 4 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆28Updated 8 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆16Updated 6 months ago
• StanfordAHA / CGRAGenerator
  ☆19Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆74Updated 3 weeks ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆45Updated 7 years ago