CTSRD-CHERI / axe

Related projects ⓘ

Alternatives and complementary repositories for axe

• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆17Updated 4 years ago
• riscv / riscv-test-env
  ☆40Updated 5 months ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆33Updated 4 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆26Updated this week
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 4 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆34Updated 8 months ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆78Updated 4 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆46Updated 7 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆135Updated last month
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆40Updated 6 years ago
• esperantotech / boom-template
  A template for building new projects/platforms using the BOOM core.
  ☆24Updated 5 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 7 years ago
• tymonx / virtio
  Virtio implementation in SystemVerilog
  ☆46Updated 6 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆17Updated 8 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 2 weeks ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆33Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 2 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆71Updated 9 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated last month
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆29Updated last month
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆47Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated last year
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆30Updated 10 months ago
• IBM / perfect-chisel
  Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
  ☆30Updated last year
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆67Updated 4 years ago