hotwolf / WbXbcLinks
HDL components to build a customized Wishbone crossbar switch
☆14Updated 6 years ago
Alternatives and similar repositories for WbXbc
Users that are interested in WbXbc are comparing it to the libraries listed below
Sorting:
- Wishbone interconnect utilities☆41Updated 5 months ago
- This is a circular buffer controller used in FPGA.☆34Updated 9 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated this week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆17Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆28Updated 5 years ago
- Portable HyperRAM controller☆56Updated 7 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆35Updated 8 months ago
- SDRAM controller with multiple wishbone slave ports☆29Updated 6 years ago
- Wishbone to AXI bridge (VHDL)☆42Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 4 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Updated 12 years ago
- DDR3 SDRAM controller☆18Updated 11 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- ☆59Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- Digital Interpolation Techniques Applied to Digital Signal Processing☆62Updated last year
- PCI bridge☆18Updated 11 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated last week
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆14Updated 3 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 7 months ago