hotwolf / WbXbcLinks
HDL components to build a customized Wishbone crossbar switch
☆14Updated 6 years ago
Alternatives and similar repositories for WbXbc
Users that are interested in WbXbc are comparing it to the libraries listed below
Sorting:
- ☆60Updated 4 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆29Updated 5 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32Updated 2 years ago
- Wishbone interconnect utilities☆43Updated 9 months ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- ☆71Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Wishbone to AXI bridge (VHDL)☆43Updated 6 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆61Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Updated 12 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 8 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- ☆38Updated 11 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆38Updated 10 months ago
- ☆14Updated 7 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆79Updated 3 weeks ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆32Updated last year
- Mathematical Functions in Verilog☆95Updated 4 years ago
- M-extension for RISC-V cores.☆31Updated 11 months ago
- Portable HyperRAM controller☆60Updated 11 months ago
- This is a circular buffer controller used in FPGA.☆34Updated 9 years ago
- UART models for cocotb☆31Updated 2 months ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆81Updated last year
- Example Verilog code for Ulx3s☆42Updated 3 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆20Updated 3 months ago