Alternatives and similar repositories for prjxray:

Users that are interested in prjxray are comparing it to the libraries listed below

• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,276Updated 2 weeks ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆453Updated 3 weeks ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆334Updated 2 weeks ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆411Updated this week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆410Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆618Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆551Updated 3 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆682Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,425Updated this week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆578Updated 4 years ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆633Updated last month
• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆541Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆385Updated 4 months ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,053Updated last month
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆282Updated this week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆397Updated 2 weeks ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆768Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆649Updated 5 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆570Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆903Updated last week
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆427Updated 7 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆608Updated 2 weeks ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆238Updated last week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,315Updated this week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆638Updated 3 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆405Updated 2 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,085Updated this week
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆271Updated 8 months ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆651Updated this week