Alternatives and similar repositories for openFPGALoader

Users that are interested in openFPGALoader are comparing it to the libraries listed below

• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,204Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,532Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,659Updated last week
• YosysHQ / apicula
  Project Apicula 🐝: bitstream documentation for Gowin FPGAs
  ☆589Updated this week
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆901Updated this week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,882Updated last week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,344Updated 2 weeks ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆665Updated last month
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆802Updated last week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,099Updated last month
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆830Updated 4 months ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆853Updated 4 months ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,011Updated this week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,824Updated last week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆679Updated last week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,568Updated this week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆792Updated 2 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆424Updated 2 years ago
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,308Updated 3 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,117Updated this week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆658Updated last month
• Obijuan / open-fpga-verilog-tutorial
  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
  ☆827Updated 5 years ago
• litex-hub / litex-boards
  LiteX boards files
  ☆440Updated last week
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,205Updated last year
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆447Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆670Updated 4 months ago
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆679Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆672Updated 3 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆409Updated 9 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,646Updated last month