Alternatives and similar repositories for nextpnr

Users that are interested in nextpnr are comparing it to the libraries listed below

• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,088Updated 2 months ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,142Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,325Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,390Updated 2 weeks ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆820Updated 2 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,630Updated 2 months ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,994Updated this week
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,301Updated 2 months ago
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,836Updated this week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆655Updated last month
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆718Updated 7 months ago
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆881Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆984Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,451Updated 2 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,065Updated this week
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆424Updated 3 months ago
• nickg / nvc
  VHDL compiler and simulator
  ☆729Updated last week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆676Updated 3 years ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,132Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,615Updated this week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆785Updated 2 weeks ago
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,767Updated 3 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,330Updated last year
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆673Updated 2 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆707Updated last month
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆821Updated 2 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,849Updated last month
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆938Updated last month
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,840Updated this week