YosysHQ / nextpnr
nextpnr portable FPGA place and route tool
☆1,420Updated this week
Alternatives and similar repositories for nextpnr:
Users that are interested in nextpnr are comparing it to the libraries listed below
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,050Updated 3 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,267Updated this week
- Documenting the Xilinx 7-series bit-stream format.☆796Updated this week
- Universal utility for programming FPGA☆1,308Updated this week
- SERV - The SErial RISC-V CPU☆1,559Updated last month
- Linux on LiteX-VexRiscv☆628Updated 3 weeks ago
- A Python toolbox for building complex digital hardware☆1,269Updated 2 months ago
- Yosys Open SYnthesis Suite☆3,754Updated this week
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆638Updated 3 months ago
- A small, light weight, RISC CPU soft core☆1,385Updated 2 months ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆669Updated 3 years ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,025Updated this week
- Documenting the Lattice ECP5 bit-stream format.☆411Updated 2 weeks ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆649Updated 5 months ago
- An open-source static random access memory (SRAM) compiler.☆891Updated 3 weeks ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,732Updated 2 months ago
- FOSS Flow For FPGA☆384Updated 3 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,514Updated 2 weeks ago
- An abstraction library for interfacing EDA tools☆684Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆616Updated 2 weeks ago
- VeeR EH1 core☆869Updated last year
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆426Updated 7 months ago
- Verilog library for ASIC and FPGA designers☆1,275Updated 11 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆444Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,049Updated 2 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,078Updated this week
- An Open-source FPGA IP Generator☆898Updated this week
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆647Updated this week
- A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …☆1,734Updated this week
- cocotb: Python-based chip (RTL) verification☆1,950Updated last week