Alternatives and similar repositories for OpenFPGA

Users that are interested in OpenFPGA are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆912Updated 2 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,145Updated 6 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆847Updated 4 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,414Updated 2 weeks ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆966Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,692Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆677Updated 2 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆677Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆609Updated 7 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,367Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆945Updated last year
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆843Updated 9 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,369Updated last year
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆734Updated 10 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆748Updated 3 weeks ago
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆821Updated last week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆724Updated 2 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆524Updated last year
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆674Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆622Updated 2 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,167Updated this week
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆433Updated 3 years ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,108Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,174Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,701Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,133Updated 4 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆676Updated 4 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆660Updated 9 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆469Updated 3 weeks ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆599Updated 4 months ago