lnis-uofu / OpenFPGA
An Open-source FPGA IP Generator
☆882Updated this week
Alternatives and similar repositories for OpenFPGA:
Users that are interested in OpenFPGA are comparing it to the libraries listed below
- An abstraction library for interfacing EDA tools☆669Updated last week
- Bus bridges and other odds and ends☆523Updated last month
- Various HDL (Verilog) IP Cores☆751Updated 3 years ago
- Common SystemVerilog components☆587Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,233Updated 3 weeks ago
- SystemVerilog to Verilog conversion☆601Updated 3 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,252Updated last week
- An open-source static random access memory (SRAM) compiler.☆881Updated 4 months ago
- A Linux-capable RISC-V multicore for and by the world☆667Updated 2 weeks ago
- A list of resources related to the open-source FPGA projects☆400Updated 2 years ago
- Verilog AXI stream components for FPGA implementation☆790Updated 2 weeks ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆575Updated 4 years ago
- SERV - The SErial RISC-V CPU☆1,504Updated 2 weeks ago
- VeeR EH1 core☆860Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆423Updated 3 years ago
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆631Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,023Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆559Updated last week
- Verilog PCI express components☆1,243Updated 10 months ago
- cocotb: Python-based chip (RTL) verification☆1,917Updated this week
- A huge VHDL library for FPGA development☆380Updated this week
- Linux on LiteX-VexRiscv☆616Updated last week
- 32-bit Superscalar RISC-V CPU☆961Updated 3 years ago
- Multi-platform nightly builds of open source digital design and verification tools☆984Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,491Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆460Updated last month
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆481Updated 3 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆647Updated 4 months ago
- ☆422Updated 2 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago