lnis-uofu / OpenFPGALinks
An Open-source FPGA IP Generator
☆1,026Updated last week
Alternatives and similar repositories for OpenFPGA
Users that are interested in OpenFPGA are comparing it to the libraries listed below
Sorting:
- An open-source static random access memory (SRAM) compiler.☆975Updated 2 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,179Updated this week
- VeeR EH1 core☆914Updated 2 years ago
- Bus bridges and other odds and ends☆612Updated 8 months ago
- A list of resources related to the open-source FPGA projects☆433Updated 3 years ago
- Modular hardware build system☆1,113Updated this week
- An abstraction library for interfacing EDA tools☆731Updated last week
- SystemVerilog to Verilog conversion☆686Updated last month
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆531Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,437Updated 2 weeks ago
- FOSS Flow For FPGA☆415Updated 11 months ago
- Common SystemVerilog components☆689Updated this week
- Various HDL (Verilog) IP Cores☆854Updated 4 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆627Updated this week
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆737Updated 11 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,152Updated 6 months ago
- A Linux-capable RISC-V multicore for and by the world☆751Updated last month
- Open Logic FPGA Standard Library☆833Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,704Updated 3 weeks ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆678Updated 5 months ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,281Updated this week
- Linux on LiteX-VexRiscv☆672Updated 3 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆949Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,376Updated last week
- Verilog library for ASIC and FPGA designers☆1,377Updated last year
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆604Updated 7 years ago
- SERV - The SErial RISC-V CPU☆1,711Updated last week
- 32-bit Superscalar RISC-V CPU☆1,154Updated 4 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆678Updated last week
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆599Updated 4 months ago