Alternatives and similar repositories for OpenFPGA:

Users that are interested in OpenFPGA are comparing it to the libraries listed below

• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,234Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆523Updated last month
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆876Updated 3 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆668Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆583Updated last week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,061Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆789Updated last week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,023Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆598Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆858Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆666Updated last week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆956Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,487Updated 2 weeks ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆748Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆646Updated 3 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,250Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,258Updated 10 months ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,236Updated 10 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆558Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,281Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆977Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆375Updated 2 months ago
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆378Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆584Updated last week
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,633Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,502Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,074Updated last month
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆670Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆502Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆786Updated this week