lnis-uofu / OpenFPGALinks
An Open-source FPGA IP Generator
☆1,039Updated this week
Alternatives and similar repositories for OpenFPGA
Users that are interested in OpenFPGA are comparing it to the libraries listed below
Sorting:
- SystemVerilog to Verilog conversion☆693Updated last month
- An open-source static random access memory (SRAM) compiler.☆985Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,158Updated 7 months ago
- An abstraction library for interfacing EDA tools☆737Updated 3 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,735Updated 3 weeks ago
- Common SystemVerilog components☆694Updated 3 weeks ago
- Bus bridges and other odds and ends☆618Updated 9 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,453Updated last month
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆533Updated last year
- VeeR EH1 core☆918Updated 2 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆678Updated 5 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,381Updated 3 weeks ago
- Open Logic FPGA Standard Library☆841Updated last week
- Modular hardware build system☆1,119Updated this week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆682Updated last month
- Various HDL (Verilog) IP Cores☆859Updated 4 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,184Updated this week
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆741Updated 11 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆632Updated 3 weeks ago
- SERV - The SErial RISC-V CPU☆1,726Updated last week
- 32-bit Superscalar RISC-V CPU☆1,169Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆557Updated 2 months ago
- lowRISC Style Guides☆474Updated 2 months ago
- A list of resources related to the open-source FPGA projects☆435Updated 3 years ago
- The OpenPiton Platform☆758Updated 3 months ago
- RISC-V Cores, SoC platforms and SoCs☆907Updated 4 years ago
- FOSS Flow For FPGA☆420Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆951Updated last year
- Functional verification project for the CORE-V family of RISC-V cores.☆636Updated this week
- Multi-platform nightly builds of open source digital design and verification tools☆1,311Updated this week