Documenting the Lattice ECP5 bit-stream format.
☆452Feb 26, 2026Updated last month
Alternatives and similar repositories for prjtrellis
Users that are interested in prjtrellis are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- nextpnr portable FPGA place and route tool☆1,647Apr 9, 2026Updated last week
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,150Feb 26, 2026Updated last month
- Documenting Lattice's 28nm FPGA parts☆149Feb 26, 2026Updated last month
- Documenting the Xilinx 7-series bit-stream format.☆869Jun 5, 2025Updated 10 months ago
- Yosys Open SYnthesis Suite☆4,397Updated this week
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ECP5 breakout board in a feather physical format☆526Nov 6, 2024Updated last year
- PCB for ULX3S FPGA R&D board☆425Apr 27, 2025Updated 11 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102May 16, 2023Updated 2 years ago
- 妖刀夢渡☆63Apr 2, 2019Updated 7 years ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆684Jan 8, 2022Updated 4 years ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆314May 25, 2023Updated 2 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Jan 22, 2022Updated 4 years ago
- Ultimate ECP5 development board☆116Jul 4, 2019Updated 6 years ago
- Multi-platform nightly builds of open source FPGA tools☆301Nov 3, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Universal utility for programming FPGA☆1,590Apr 10, 2026Updated last week
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆656Updated this week
- A modern hardware definition language and toolchain based on Python☆1,987Apr 10, 2026Updated last week
- Build your hardware, easily!☆3,835Apr 8, 2026Updated last week
- Visual editor for open FPGA boards☆1,891Feb 16, 2026Updated 2 months ago
- Project Trellis database☆14Sep 15, 2025Updated 7 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆501Apr 9, 2026Updated last week
- A Python toolbox for building complex digital hardware☆1,321Jan 5, 2026Updated 3 months ago
- Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)☆259Aug 21, 2023Updated 2 years ago
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Place and route tool for FPGAs☆422Jul 28, 2019Updated 6 years ago
- Documenting the Anlogic FPGA bit-stream format.☆88Dec 25, 2022Updated 3 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆93Nov 7, 2024Updated last year
- LiteX boards files☆476Apr 3, 2026Updated 2 weeks ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆305Apr 9, 2026Updated last week
- Bootloader for Fomu☆105Dec 31, 2022Updated 3 years ago
- ☆12Jun 4, 2021Updated 4 years ago
- FPGA USB stack written in LiteX☆134Jun 5, 2022Updated 3 years ago
- Small and low cost FPGA educational and development board☆671Feb 10, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An open source USB bootloader for FPGAs☆397Sep 15, 2023Updated 2 years ago
- Small, but powerful FPGA development board based on the Lattice ECP5.☆75Jun 2, 2019Updated 6 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- SERV - The SErial RISC-V CPU☆1,785Feb 19, 2026Updated last month
- Experimental flows using nextpnr for Xilinx devices☆255Oct 11, 2024Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆59May 26, 2023Updated 2 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆419Apr 10, 2026Updated last week