Alternatives and similar repositories for amaranth

Users that are interested in amaranth are comparing it to the libraries listed below

• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆669Updated 3 years ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,431Updated this week
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,271Updated last week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,324Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,044Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,578Updated this week
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,759Updated this week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,299Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,281Updated 3 weeks ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,058Updated last month
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,360Updated last month
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆844Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,756Updated 3 weeks ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆988Updated this week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆653Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆797Updated this week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆635Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,784Updated this week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,024Updated 3 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,398Updated 3 months ago
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆640Updated 3 months ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆411Updated 2 weeks ago
• YosysHQ / apicula
  Project Apicula 🐝: bitstream documentation for Gowin FPGAs
  ☆552Updated this week
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,798Updated this week
• nickg / nvc
  VHDL compiler and simulator
  ☆692Updated this week
• myhdl / myhdl
  The MyHDL development repository
  ☆1,076Updated last month
• BrunoLevy / learn-fpga
  Learning FPGA, yosys, nextpnr, and RISC-V
  ☆2,794Updated 2 months ago
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,157Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆386Updated 4 months ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,473Updated 10 months ago