Alternatives and similar repositories for vtr-verilog-to-routing

Users that are interested in vtr-verilog-to-routing are comparing it to the libraries listed below

• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆936Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆659Updated 2 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,325Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,058Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆981Updated last week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,353Updated last week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆813Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆598Updated 2 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆707Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,330Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,109Updated 2 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,609Updated 2 weeks ago
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆739Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆649Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆582Updated 4 months ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,615Updated last week
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆496Updated last week
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆664Updated 2 years ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆784Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆889Updated 2 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,153Updated 2 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆819Updated 5 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆634Updated 3 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆509Updated 8 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆448Updated 2 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆464Updated 2 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆525Updated 2 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆438Updated 3 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆607Updated 3 years ago