Verilog to Routing -- Open Source CAD Flow for FPGA Research
☆1,226May 6, 2026Updated this week
Alternatives and similar repositories for vtr-verilog-to-routing
Users that are interested in vtr-verilog-to-routing are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Yosys Open SYnthesis Suite☆4,433Updated this week
- An Open-source FPGA IP Generator☆1,097Updated this week
- Build Customized FPGA Implementations for Vivado☆371Apr 29, 2026Updated last week
- nextpnr portable FPGA place and route tool☆1,663Updated this week
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Apr 8, 2026Updated last month
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆46Sep 13, 2024Updated last year
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,160Updated this week
- OpenSTA engine☆576Apr 30, 2026Updated last week
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,647Updated this week
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆92Feb 11, 2020Updated 6 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆306Updated this week
- A High-performance Timing Analysis Tool for VLSI Systems☆694Dec 26, 2025Updated 4 months ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,778Mar 25, 2026Updated last month
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆114Mar 9, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Deep learning toolkit-enabled VLSI placement☆988Apr 24, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆459Apr 5, 2026Updated last month
- Documenting the Xilinx 7-series bit-stream format.☆879Jun 5, 2025Updated 11 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆175Apr 25, 2025Updated last year
- Open-source FPGA research and prototyping framework.☆211Aug 8, 2024Updated last year
- An abstraction library for interfacing EDA tools☆765Apr 24, 2026Updated 2 weeks ago
- Icarus Verilog☆3,434May 4, 2026Updated last week
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆94Apr 30, 2025Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,587Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SystemVerilog to Verilog conversion☆725Mar 28, 2026Updated last month
- ☆114Feb 2, 2021Updated 5 years ago
- An open-source static random access memory (SRAM) compiler.☆1,052Apr 30, 2026Updated last week
- FPGA Assembly (FASM) Parser and Generator☆102Jul 25, 2022Updated 3 years ago
- RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017.☆43Dec 14, 2019Updated 6 years ago
- Example designs showing different ways to use F4PGA toolchains.☆287Mar 27, 2024Updated 2 years ago
- Showcase examples for EPFL logic synthesis libraries☆205Apr 5, 2024Updated 2 years ago
- C++ logic network library☆290Updated this week
- Modular hardware build system☆1,156May 4, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆255Feb 22, 2026Updated 2 months ago
- FPGA tool performance profiling☆107Feb 24, 2024Updated 2 years ago
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,515Oct 28, 2024Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,413Feb 13, 2026Updated 2 months ago
- Place and route tool for FPGAs☆422Jul 28, 2019Updated 6 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,834Mar 13, 2026Updated last month
- XLS: Accelerated HW Synthesis☆1,481May 2, 2026Updated last week