f4pga / prjxray-db
Project X-Ray Database: XC7 Series
☆67Updated 3 years ago
Alternatives and similar repositories for prjxray-db:
Users that are interested in prjxray-db are comparing it to the libraries listed below
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- FuseSoC standard core library☆134Updated last month
- A wishbone controlled scope for FPGA's☆81Updated last year
- Test of the USB3 IP Core from Daisho on a Xilinx device☆90Updated 5 years ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆121Updated 8 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆54Updated last year
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆76Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆178Updated 4 months ago
- VHDL library 4 FPGAs☆177Updated this week
- ☆36Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆138Updated 2 years ago
- ☆112Updated 4 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆43Updated last year
- Demo SoC for SiliconCompiler.☆59Updated last month
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 3 years ago
- An Open Source configuration of the Arty platform☆130Updated last year
- Naive Educational RISC V processor☆82Updated 6 months ago
- Mutation Cover with Yosys (MCY)☆80Updated last week
- Yet Another RISC-V Implementation☆93Updated 7 months ago
- Wishbone interconnect utilities☆40Updated 2 months ago
- ☆78Updated last year
- assorted library of utility cores for amaranth HDL☆87Updated 7 months ago