Project X-Ray Database: XC7 Series
☆77Dec 14, 2021Updated 4 years ago
Alternatives and similar repositories for prjxray-db
Users that are interested in prjxray-db are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Documenting the Xilinx 7-series bit-stream format.☆915Jun 5, 2025Updated last year
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 4 months ago
- A Verilog Synthesis Regression Test☆39Jan 19, 2026Updated 8 months ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆19Apr 6, 2022Updated 4 years ago
- ☆106Jun 27, 2022Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- A multiply core generator☆16Jun 25, 2020Updated 6 years ago
- Generate bitstream from FPGA assembly.☆29Updated this week
- Project Trellis database☆14Sep 15, 2025Updated last year
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- Experimental flows using nextpnr for Xilinx devices☆268Oct 11, 2024Updated last year
- XC2064 bitstream documentation☆18Sep 24, 2018Updated 8 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Oct 24, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FPGA Assembly (FASM) Parser and Generator☆104Jul 25, 2022Updated 4 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 8 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆314Updated this week
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆39Aug 21, 2024Updated 2 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆86Feb 9, 2022Updated 4 years ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆59Apr 8, 2023Updated 3 years ago
- Small footprint and configurable video cores (Deprecated)☆75Sep 15, 2021Updated 5 years ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- PCIe adapter for an FPGA accelerator for Open CloudServer☆26May 31, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Native Rust support for AMD Zynq 7000 SoC bare-metal programming☆22Sep 15, 2026Updated last week
- Documenting Lattice's 28nm FPGA parts☆154Jul 19, 2026Updated 2 months ago
- 360nosc0pe Yocto build environment☆13Aug 27, 2018Updated 8 years ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 3 years ago
- Experimental flows using nextpnr for Xilinx devices☆71Updated this week
- ☆22Jul 28, 2016Updated 10 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆63Mar 16, 2023Updated 3 years ago
- photonSDI - an open source SDI core☆11May 26, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- [MIGRATED to https://codeberg.org/prjunnamed/prjcombine/] An FPGA reverse engineering and documentation project☆66Mar 12, 2026Updated 6 months ago
- Bitstream Fault Analysis Tool☆16Jul 17, 2023Updated 3 years ago
- Yosys Plugins☆22Jul 16, 2019Updated 7 years ago
- Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx☆95Jun 10, 2015Updated 11 years ago
- ☆15Jul 28, 2016Updated 10 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆36Jul 15, 2024Updated 2 years ago
- Firmware and Gateware for the DiVA platform.☆14Sep 8, 2025Updated last year