f4pga / prjxray-dbLinks
Project X-Ray Database: XC7 Series
☆69Updated 3 years ago
Alternatives and similar repositories for prjxray-db
Users that are interested in prjxray-db are comparing it to the libraries listed below
Sorting:
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated 3 weeks ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆78Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆179Updated 5 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- FuseSoC standard core library☆143Updated 3 weeks ago
- An Open Source configuration of the Arty platform☆129Updated last year
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A wishbone controlled scope for FPGA's☆82Updated last year
- Mutation Cover with Yosys (MCY)☆84Updated 2 weeks ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- System on Chip toolkit for Amaranth HDL☆91Updated 8 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- Extensible FPGA control platform☆62Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago
- ☆79Updated last year
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆92Updated 5 years ago
- PicoRV☆44Updated 5 years ago
- Naive Educational RISC V processor☆84Updated 2 weeks ago
- Demo SoC for SiliconCompiler.☆59Updated 3 weeks ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago