Cyclone V bitstream reverse-engineering project
☆134Oct 19, 2023Updated 2 years ago
Alternatives and similar repositories for mistral
Users that are interested in mistral are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Documenting Lattice's 28nm FPGA parts☆153Feb 26, 2026Updated 4 months ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 6 years ago
- Experimental flows using nextpnr for Xilinx devices☆260Oct 11, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- 妖刀夢渡☆64Apr 2, 2019Updated 7 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated 4 months ago
- Documenting the Microchip (Atmel) ATF15xx CPLD fuse maps and programming algorithms☆59Jun 10, 2025Updated last year
- Documenting the Anlogic FPGA bit-stream format.☆90Dec 25, 2022Updated 3 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 8 years ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjcombine/] An FPGA reverse engineering and documentation project☆65Mar 12, 2026Updated 3 months ago
- nextpnr portable FPGA place and route tool☆1,699Jun 21, 2026Updated last week
- SD device emulator from ProjectVault☆21Sep 24, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 4 months ago
- ☆22Mar 5, 2022Updated 4 years ago
- The Critical Path - a rambly FPGA blog☆51Sep 4, 2020Updated 5 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆83Feb 9, 2022Updated 4 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- ☆10Nov 6, 2018Updated 7 years ago
- A padring generator for ASICs☆26May 17, 2023Updated 3 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Mar 19, 2026Updated 3 months ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Documenting the Xilinx 7-series bit-stream format.☆897Jun 5, 2025Updated last year
- RISC-V Assembly with a C wrapper☆12Sep 23, 2019Updated 6 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆103May 16, 2023Updated 3 years ago
- Resource-efficient 16-bit CPU architecture for FPGA control plane☆97Feb 20, 2025Updated last year
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 7 years ago
- MicroPython - legacy branch contain old experiments, and experimental for new work☆33Sep 6, 2021Updated 4 years ago
- Use ECP5 JTAG port to interact with user design☆33Jul 23, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Low-cost ECP5 FPGA development board☆80Sep 1, 2020Updated 5 years ago
- An attempt to reverse engineer a bitstream made for an AL3-10 FPGA☆16Jan 6, 2023Updated 3 years ago
- Simple peripheral library for CH55x microcontrolles☆16May 4, 2021Updated 5 years ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆19Apr 6, 2022Updated 4 years ago
- Read out firmware of some STM32 parts☆15Jul 20, 2025Updated 11 months ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago